PD Dr.-Ing. Frank Hannig
Technische Fakultät
Privatdozentinnen und Privatdozenten
Adresse
Cauerstraße 1191058 Erlangen
Kontakt
Curriculum Vitæ
1974
born in Verl, Germany
2000
Diploma degree in EE/CS (interdisciplinary course of study), University of Paderborn, Germany
11/2000 – 12/2002
Researcher at the Computer Engineering Laboratory (Institute DATE), University of Paderborn
since 01/2003
Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
since 2004
Head of the Architecture and Compiler Design Group at the Department of Computer Science 12 (Hardware-Software-Co-Design), Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany
08/2009
Dr.-Ing. degree in CS, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany,
Thesis: „Scheduling Techniques for High-Throughput Loop Accelerators“
07/2018
Habilitation (Dr.-Ing. habil.), Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany,
Thesis: „Domain-specific and Resource-aware Computing“
Experience
C-LAB,
Paderborn, Germany
01/1997 – 04/1999
Working student at C-LAB (Cooperative Computing & Communication Laboratory) in the research of analysing crosstalk noise problems during the design of digital high-speed integrated circuits
Electrolux,
Fredericia, Denmark
04/1999 – 09/1999
Practical training at Electrolux GPDH Tech-Centre, primary development, hardware/software co-design of electrical hobs
C-LAB,
Paderborn, Germany
10/1999 – 04/2000
Working student at C-LAB in the research group OIT (Optical Interconnection Technology)
Professional Scientific Activities
Editorships
- Associate Editor – IEEE Embedded Systems Letters (ESL)
- Associate Editor – Journal of Real-Time Image Processing – Springer
Conference and Workshop Organization
- Initiator and General Co-Chair, SLOHA 2021 – DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures, co-located with Conference on Design, Automation and Test in Europe (DATE)
- Programme Chair, ARC 2021 – International Symposium on Applied Reconfigurable Computing
- Global Chair Topic 1: Compilers, Tools and Environments, Euro-Par 2021 – 27th International European Conference on Parallel and Distributed Computing
- Programme Co-Chair, ASAP 2020 – 31st IEEE International Conference on Application-specific Systems, Architectures and Processors
- Local Arrangement and ICT Co-Chair, DATE 2019 – Conference on Design, Automation and Test in Europe
- Topic Chair E2: Compilers and Software Synthesis, DATE 2018 – Conference on Design, Automation and Test in Europe
- Topic Chair E2: Compilers and Software Synthesis for Embedded Systems, DATE 2017 – Conference on Design, Automation and Test in Europe
- Program Chair, ARCS 2016 – 29th GI/ITG International Conference on Architecture of Computing Systems
- Topic Co-Chair E2: Compilers and Software Synthesis for Embedded Systems, DATE 2016 – Conference on Design, Automation and Test in Europe
- General Co-Chair, FSP 2015 – Second International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
- Initiator and General Co-Chair, HIS 2015 – DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems, co-located with Conference on Design, Automation and Test in Europe (DATE)
- Initiator and General Co-Chair, FSP 2014 – First International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
- Co-Organizer and Program Chair, Racing 2014 – Workshop on Resource-Awareness and Adaptivity in Multi-Core Computing, co-located with IEEE European Test Symposium (ETS)
- Publication Chair, ASAP 2011 – 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
- Publication Chair, ASAP 2010 – 21th IEEE International Conference on Application-specific Systems, Architectures and Processors
- Organization Assistance, CODES+ISSS 2007 – International Conference on Hardware-Software Codesign and System Synthesis
- Organization Assistance, Euro-Par 2006 – European Conference on Parallel Computing
- Organization Assistance, ARCS 2006 – 19th International Conference on Architecture of Computing Systems
Program Committee Member
- ARC 2025 – International Symposium on Applied Reconfigurable Computing
- ASAP 2025 – 36th IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2025 – International Conference on Hardware/Software Codesign and System Synthesis
- DAC 2025 – 62nd Design Automation Conference
- DASIP 2025 – Workshop on Design and Architectures for Signal and Image Processing
- DATE 2025 – Conference on Design, Automation and Test in Europe
- LCTES 2025 – 26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems
- MATTERV 2025 – Special Session at DSD 2025 on Opensource Methods, Architectures, Tools and Technologies for RISC-V
- SAC 2025 – 40th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2025 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- CODES+ISSS 2024 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2024 – Workshop on Design and Architectures for Signal and Image Processing
- LCTES 2024 – 25th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems
- MATTERV 2024 – Special Session at DSD 2024 on Opensource Methods, Architectures, Tools and Technologies for RISC-V
- NeuroEdge 2024 – Workshop on Efficient AI at the Edge
- SAC 2024 – 39th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2024 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- ARC 2023 – International Symposium on Applied Reconfigurable Computing
- ASAP 2023 – 34th IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2023 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2023 – Workshop on Design and Architectures for Signal and Image Processing
- SAC 2023 – 38th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2023 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- ASAP 2022 – 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2022 – International Conference on Hardware/Software Codesign and System Synthesis
- DAC 2022 – 59th Design Automation Conference
- DASIP 2022 – Workshop on Design and Architectures for Signal and Image Processing
- DATE 2022 – Conference on Design, Automation and Test in Europe
- LCTES 2022 – 23rd ACM SIGPLAN/SIGBED International Conference on Languages Compilers, Tools and Theory of Embedded Systems
- SAC 2022 – 37th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2022 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- ARC 2021 – International Symposium on Applied Reconfigurable Computing
- ASAP 2021 – 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2021 – International Conference on Hardware/Software Codesign and System Synthesis
- DAC 2021 – 58th Design Automation Conference
- DASIP 2021 – Workshop on Design and Architectures for Signal and Image Processing
- DATE 2021 – Conference on Design, Automation and Test in Europe
- Euro-Par 2021 – 27th International European Conference on Parallel and Distributed Computing, Topic 1: Compilers, Tools and Environments
- SAC 2021 – 36th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2021 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2021 – 24th International Workshop on Software and Compilers for Embedded Systems
- ARC 2020 – International Symposium on Applied Reconfigurable Computing
- ASAP 2020 – 31st IEEE International Conference on Application-specific Systems, Architectures and Processors
- CF 2020 – ACM International Conference on Computing Frontiers
- CODES+ISSS 2020 – International Conference on Hardware/Software Codesign and System Synthesis
- DAC 2020 – 57th Design Automation Conference
- DATE 2020 – Conference on Design, Automation and Test in Europe
- SAC 2020 – 35th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2020 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2020 – 23rd International Workshop on Software and Compilers for Embedded Systems
- APPMM 2019 – 8th International Workshop on Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era
- ARC 2019 – International Symposium on Applied Reconfigurable Computing
- CF 2019 – ACM International Conference on Computing Frontiers
- CODES+ISSS 2019 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2019 – Conference on Design and Architectures for Signal and Image Processing
- FSP 2019 – 6th International Workshop on FPGAs for Software Programmers
- LCTES 2019 – International Conference on Languages Compilers, Tools and Theory of Embedded Systems
- ParaFPGA 2019 – Mini-Symposium on Parallel Computing with FPGAs
- SAC 2019 – 34th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2019 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2019 – 22nd International Workshop on Software and Compilers for Embedded Systems
- ARC 2018 – International Symposium on Applied Reconfigurable Computing
- CF 2018 – ACM International Conference on Computing Frontiers
- CODES+ISSS 2018 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2018 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2018 – Conference on Design, Automation and Test in Europe
- Euro-Par 2018 – 24th International European Conference on Parallel and Distributed Computing, Topic 4: High Performance Architectures and Compilers
- FSP 2018 – 5th International Workshop on FPGAs for Software Programmers
- SAC 2018 – 33rd ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2018 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2018 – 21st International Workshop on Software and Compilers for Embedded Systems
- ARC 2017 – International Symposium on Applied Reconfigurable Computing
- CODES+ISSS 2017 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2017 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2017 – Conference on Design, Automation and Test in Europe
- FSP 2017 – 4th International Workshop on FPGAs for Software Programmers
- ParaFPGA 2017 – Mini-Symposium on Parallel Computing with FPGAs
- SAC 2017 – 32nd ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2017 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2017 – 20th International Workshop on Software and Compilers for Embedded Systems
- UCHPC 2017 – 10th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2017
- ARC 2016 – International Symposium on Applied Reconfigurable Computing
- ASAP 2016 – 27th IEEE International Conference on Application-specific Systems, Architectures and Processors
- ASR-MOV 2016 – International Workshop on Architectures and Systems for Real-time Mobile Vision applications
- CODES+ISSS 2016 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2016 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2016 – Conference on Design, Automation and Test in Europe
- FSP 2016 – Third International Workshop on FPGAs for Software Programmers
- DLMCS 2016 – Workshop on Data Locality in Modern Computing Systems
- ISC 2016 – International Supercomputing Conference
- SAC 2016 – 31st ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2016 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2016 – 19th International Workshop on Software and Compilers for Embedded Systems
- UCHPC 2016 – 9th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2016
- VLSID 2016 – 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, Track D1: System-level Design
- ARC 2015 – International Symposium on Applied Reconfigurable Computing
- ASAP 2015 – 26th IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2015 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2015 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2015 – Conference on Design, Automation and Test in Europe
- HiStencils 2015 – 2nd International Workshop on High-Performance Stencil Computations
- ISC 2015 – International Supercomputing Conference
- SAC 2015 – 30th ACM/SIGAPP Symposium On Applied Computing, Embedded Systems Track
- SAMOS 2015 – International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
- SCOPES 2015 – 18th International Workshop on Software and Compilers for Embedded Systems
- UCHPC 2015 – 8th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2015
- ARC 2014 – International Symposium on Applied Reconfigurable Computing
- ASAP 2014 – 25th IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2014 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2014 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2014 – Conference on Design, Automation and Test in Europe
- EUC 2014 – The 12th IEEE International Conference on Embedded and Ubiquitous Computing
- HiStencils 2014 – 1st International Workshop on High-Performance Stencil Computations
- ISC 2014 – International Supercomputing Conference
- ODES 2014 – 11th Workshop on Optimizations for DSP and Embedded Systems
- SAC 2014 – 29th ACM Symposium on Applied Computing, Embedded Systems Track
- UCHPC 2014 – 7th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2014
- ARC 2013 – International Symposium on Applied Reconfigurable Computing
- ASAP 2013 – 24th IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2013 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2013 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2013 – Conference on Design, Automation and Test in Europe
- ISC 2013 – International Supercomputing Conference
- SAC 2013 – 28th ACM Symposium on Applied Computing, Embedded Systems Track
- UCHPC 2013 – 6th Workshop on UnConventional High Performance Computing in conjunction with Euro-Par 2013
- ASAP 2012 – 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2012 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2012 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2012 – Conference on Design, Automation and Test in Europe
- ERSA 2012 – International Conference on Engineering of Reconfigurable Systems and Algorithms
- SAC 2012 – 27th ACM Symposium on Applied Computing, Embedded Systems Track
- SIES 2012 – 7th IEEE International Symposium on Industrial Embedded Systems, Work-in-Progress Session
- ASAP 2011 – 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
- CODES+ISSS 2011 – International Conference on Hardware/Software Codesign and System Synthesis
- DASIP 2011 – Conference on Design and Architectures for Signal and Image Processing
- DATE 2011 – Conference on Design, Automation and Test in Europe
- ERSA 2011 – International Conference on Engineering of Reconfigurable Systems and Algorithms
Reviewing — Journals
- ACM TECS – ACM Transactions on Embedded Computing Systems
- ACM TACO – ACM Transactions on Architecture and Code Optimization
- ACM TODAES – ACM Transactions on Design Automation of Electronic Systems
- IEEE SPM – IEEE Signal Processing Magazine
- IEEE TVLSI – IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- IEEE TSP – IEEE Transactions on Signal Processing
- IEEE TCAD – IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- IEEE Design & Test – IEEE Design & Test of Computers
- EURASIP Journal on Embedded Systems
- Microprocessors and Microsystems
Reviewing — Conferences, Symposia, and Workshops (selection, in addition to TPC memberships)
- DAC (expert reviewer), ICCAD, CASES, SAMOS, ARCS, FPT, FPL, RAW, PARELEC, SiPS
Memberships
- Member of the IEEE since 2001 and Senior Member since 2012
- Affiliate member of the European Network of Excellence (NoE) on High Performance and Embedded Architecture and Compilation (HiPEAC)
- Member of the HiPEAC Reconfigurable Computing Cluster
Research Projects
Ongoing
- InvasIC: DFG Transregional Collaborative Research Centre 89 — Invasive Computing
- ExaStencils: Advanced Stencil-Code Engineering within the DFG Priority Programme 1648 (Software for Exascale Computing)
- HBS: DFG Research Training Group (Graduiertenkolleg) 1773 Heterogeneous Image Systems, Project B3
- INI.FAU: Parallelization and Resource Estimation of Algorithms for Heterogeneous DAS Architectures
- PARO: Architecture/Compiler Co-Design of Massively Parallel Processor Architectures
- MAP: Multi-core Architectures and Programming
Open Source Projects
Completed
- MMSys: Motion Management System
- CoMap: Co-Design of Massively Parallel Embedded Processor Architectures
- DFG SFB 376 — Massively Parallel Computation
- BUILDABONG: Architecture and Compiler Design for ASIPs
Education
Lectures
- Domain-Specific and Resource-Aware Computing on Multicore Architectures
- Parallel Systems
- Embedded Systems
Exercises
- Domain-Specific and Resource-Aware Computing on Multicore Architectures
- Parallel Systems
- Embedded Systems
- Hardware-Software-Co-Design
- Architecture and Design of Embedded Systems (University of Paderborn)
Seminars
- Electronic System Level Design
- Multi-Core Architectures and Programming
- Oberseminar: Hardware-Software-Co-Design
- Energy Efficient Systems
- Bluetooth (University of Paderborn)
Labs
- Unix Basics (University of Paderborn)
- Architecture Synthesis (University of Paderborn)
Publications
Statistics
- h-index (Web of Science): 17
- h-index (Scopus): 21
- h-index (Google Scholar): 31
- Erdös Number: 3 (via this path: Frank Hannig → Sándor P. Fekete → Aviezri S. Fraenkel → Paul Erdös)
2026
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Entropy Sampling-Based Neural Architecture Search for Resource-Constraint Microcontroller Targets
Conference on Design, Automation and Test in Europe (DATE) (Verona, 20. April 2026 – 22. April 2026)
BibTeX: Download
2025
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Unsupervised Learning of Variational Autoencoders on Cortex-M Microcontrollers
IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (Singapore, 15. Dezember 2025 – 18. Dezember 2025)
BibTeX: Download - , , , , :
Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units
28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Rostock, 11. März 2025 – 12. März 2025)
In: Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2025
URL: https://ieeexplore.ieee.org/document/11047216
BibTeX: Download - , , :
A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices
38th GI/ITG International Conference on Architecture of Computing Systems (Kiel, 22. April 2025 – 24. April 2025)
In: Sven Tomforde, Christian Krupitzer, Stephane Vialle, Estela Suarez, and Thilo Pionteck (Hrsg.): Architecture of Computing Systems, 38th International Conference, ARCS 2025, Kiel, Germany, April 22–24, 2025, Proceedings 2025
DOI: 10.1007/978-3-032-03281-2_12
URL: https://link.springer.com/chapter/10.1007/978-3-032-03281-2_12
BibTeX: Download - , , , :
DSL-based SNN Accelerator Design using Chisel
In: Microprocessors and Microsystems 118 (2025), Art.Nr.: 105187
ISSN: 0141-9331
DOI: j.micpro.2025.105187
BibTeX: Download - , , , :
Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks using RISC-V Custom Functional Units
In: CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems 2025
BibTeX: Download - , , , :
Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow
International Conference on Computer Aided Design (ICCAD) (Munich, 26. Oktober 2025 – 30. Oktober 2025)
In: IEEE (Hrsg.): Proceedings of the International Conference on Computer Aided Design (ICCAD) 2025
DOI: 10.1109/ICCAD66269.2025.11240834
URL: https://ieeexplore.ieee.org/document/11240834
BibTeX: Download - , , , , , , , , , , , , , , , , , , , , , , , , , , :
Special Session – Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Taipei, 28. September 2025 – 3. Oktober 2025)
In: ACM (Hrsg.): Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2025
BibTeX: Download - , , , , , :
Europractice activity report 2024
(2025), S. 29-30
URL: https://europractice-ic.com/wp-content/uploads/2025/03/Europractice_ActivityReport2024_webversion.pdf
BibTeX: Download
(Techreport) - , , , , , , :
Evaluation of CGRA Toolchains
1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) (Lyon, 31. März 2025 – 2. April 2025)
In: In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) 2025
DOI: 10.48550/arXiv.2502.19114
BibTeX: Download
2024
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Fused-Layer CNNs for Memory-Efficient Inference on Microcontrollers
Workshop on Machine Learning and Compression @ NeurIPS 2024 (Vancouver Convention Center, 10. Dezember 2024 – 15. Dezember 2024)
Open Access: https://openreview.net/forum?id=2O8qbyxH6X
BibTeX: Download - , , , :
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44 (2024), S. 1250 – 1261
ISSN: 0278-0070
DOI: 10.1109/TCAD.2024.3484354
URL: https://ieeexplore.ieee.org/document/10726519
BibTeX: Download - , , , :
Estimating the Execution Time of CNN Inference on GPUs
27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. Februar 2024 – 15. Februar 2024)
In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
BibTeX: Download - , , , , :
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers
10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Angers, 2. Mai 2024 – 4. Mai 2024)
DOI: 10.5220/0000186800003702
BibTeX: Download - , , , , :
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
In: The Computing Research Repository (CoRR), 2024
DOI: 10.48550/arXiv.2404.15833
URL: https://arxiv.org/abs/2404.15833
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(online publication) - , , , , :
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
2024 Stuttgart International Symposium on Automotive and Engine Technology (Stuttgart, 2. Juli 2024 – 3. Juli 2024)
In: André Casal Kulzer, Hans-Christian Reuss, Andreas Wagner (Hrsg.): Proceeding of the 2024 Stuttgart International Symposium on Automotive and Engine Technology, Wiesbaden: 2024
DOI: 10.1007/978-3-658-45018-2_4
BibTeX: Download - , , , , , :
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks
In: International Journal of Parallel Programming 52 (2024), S. 40 – 58
ISSN: 0885-7458
DOI: 10.1007/s10766-024-00760-5
BibTeX: Download - , , , :
Compiler-based Processor Network Generation for Neural Networks on FPGAs
27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. Februar 2024 – 15. Februar 2024)
In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
BibTeX: Download - , , , :
DSL-based SNN Accelerator Design using Chisel
27th Euromicro Conference Series on Digital System Design (DSD) (Paris, 27. August 2024 – 30. August 2024)
In: Proceedings of the 27th Euromicro Conference on Digital Systems Design (DSD) 2024
DOI: 10.1109/DSD64264.2024.00032
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SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation
20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) (Aveiro, 20. März 2024 – 22. März 2024)
In: Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) 2024
DOI: 10.1007/978-3-031-55673-9_1
BibTeX: Download - , , , , :
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
International Conference on Field Programmable Technology (FPT) (Sydney, Australia, 10. Dezember 2024 – 12. Dezember 2024)
In: IEEE (Hrsg.): Proceedings of International Conference on Field Programmable Technology (FPT) 2024
DOI: 10.1109/ICFPT64416.2024.11113397
BibTeX: Download - , , , :
Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units
Conference on Design, Automation and Test in Europe (DATE) (Valencia, 25. März 2024 – 27. März 2024)
In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2024
BibTeX: Download - , , , :
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays
35th IEEE International Conference on Application-specific Systems, Architectures and Processors (Hong Kong, 24. Juli 2024 – 26. Juli 2024)
In: Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024
DOI: 10.1109/ASAP61560.2024.00029
URL: https://ieeexplore.ieee.org/document/10631126
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ALPACA: An Accelerator Chip for Nested Loop Programs
IEEE International Symposium on Circuits and Systems (ISCAS) (Singapore, 19. Mai 2024 – 22. Mai 2024)
In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2024
DOI: 10.1109/ISCAS58744.2024.10558549
URL: https://ieeexplore.ieee.org/document/10558549
BibTeX: Download
2023
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To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations
(2023)
Open Access: https://arxiv.org/abs/2306.12742
URL: https://arxiv.org/abs/2306.12742
BibTeX: Download
(online publication) - , , , , :
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods
EuroMLSys ’23: Proceedings of the 3rd Workshop on Machine Learning and Systems (Rome, Italy, 8. Mai 2023 – 8. Mai 2023)
In: Eiko Yoneki, Luigi Nardi (Hrsg.): EuroMLSys ’23: Proceedings of the 3rd Workshop on Machine Learning and System, New York(NY) United States: 2023
DOI: 10.1145/3578356.3592595
URL: https://dl.acm.org/doi/10.1145/3578356.3592595
BibTeX: Download
2022
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Invasive Computing
FAU University Press, 2022
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download - , , , , , :
Validation and Demonstrator
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Hrsg.): Invasive Computing, FAU University Press, 2022, S. 411-431
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download - , , :
Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview
In: IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2022), S. 2661 – 2666
ISSN: 1057-7130
DOI: 10.1109/TCSII.2022.3173753
BibTeX: Download - , :
Special Issue on Applied Reconfigurable Computing
In: Journal of Signal Processing Systems (2022)
ISSN: 1939-8018
DOI: 10.1007/s11265-022-01806-y
BibTeX: Download - , , , , :
Hardware-Aware Evolutionary Filter Pruning
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. Juli 2022 – 7. Juli 2022)
DOI: 10.1007/978-3-031-15074-6_18
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MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks
The 13th International Green and Sustainable Computing Conference (IGSC) (Virtual, 24. Oktober 2022 – 27. Oktober 2022)
In: IEEE (Hrsg.): 2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC), Pittsburgh, PA, USA: 2022
DOI: 10.1109/IGSC55832.2022.9969363
URL: https://ieeexplore.ieee.org/document/9969374
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TRAC: Compilation-based Design of Transformer Accelerators for FPGAs
International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 – 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00015
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DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks
2nd European Workshop on Machine Learning and Systems (EuroMLSys) (Rennes, France, 5. April 2022 – 8. April 2022)
In: Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys), New York, NY, United States: 2022
DOI: 10.1145/3517207.3526982
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Compilation and Code Generation for Invasive Programs
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Hrsg.): Invasive Computing, FAU University Press, 2022, S. 309-333
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Invasive Tightly-Coupled Processor Arrays
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Hrsg.): Invasive Computing, FAU University Press, 2022, S. 177-202
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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2021
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HighPerMeshes — A Domain-Specific Language for Numerical Algorithms on Unstructured Grids
18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) (Warsaw, 24. August 2020 – 24. August 2020)
In: Proceedings of the 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2020: Parallel Processing Workshops 2021
DOI: 10.1007/978-3-030-71593-9_15
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The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids
In: Concurrency and Computation-Practice & Experience (2021)
ISSN: 1532-0626
DOI: 10.1002/cpe.6616
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Applied Reconfigurable Computing. Architectures, Tools, and Applications
17th International Symposium on Applied Reconfigurable Computing 2021 (Virtual Event, 29. Juni 2021 – 30. Juni 2021)
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications 2021
DOI: 10.1007/978-3-030-79025-7
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Efficient Application of Tensor Core Units for Convolving Images
24th International Workshop on Software and Compilers for Embedded Systems (Eindhoven (NL), 1. November 2021 – 2. November 2021)
In: Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems 2021
DOI: 10.1145/3493229.3493305
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Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors
In: Journal of Signal Processing Systems (2021)
ISSN: 1939-8018
DOI: 10.1007/s11265-021-01708-5
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Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021)
2021
Open Access: http://arxiv.org/html/2102.00818
URL: http://arxiv.org/abs/2102.00818
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Open Source Hardware
In: IEEE Computer 54 (2021), S. 111-115
ISSN: 0018-9162
DOI: 10.1109/MC.2021.3099046
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Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
31st International Conference on Field Programmable Logic and Applications (FPL) (Virtual Conference, 30. August 2021 – 3. September 2021)
In: Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL) 2021
DOI: 10.1109/FPL53798.2021.00079
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A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Virtual Conference, 9. Mai 2021 – 12. Mai 2021)
In: Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2021
DOI: 10.1109/FCCM51124.2021.00010
URL: https://ieeexplore.ieee.org/document/9444092
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An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning
2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (Portland, OR, 17. Mai 2021 – 21. Mai 2021)
In: Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) 2021
DOI: 10.1109/IPDPSW52791.2021.00067
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Fault-Tolerant Low-Precision DNNs using Explainable AI
Workshop on Dependable and Secure Machine Learning (DSML) (Virtual Workshop, 21. Juni 2021 – 24. Juni 2021)
In: 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) 2021
DOI: 10.1109/DSN-W52860.2021.00036
URL: https://ieeexplore.ieee.org/document/9502445/
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Symbolic Loop Compilation for Tightly Coupled Processor Arrays
In: ACM Transactions on Embedded Computing Systems (2021)
ISSN: 1539-9087
DOI: 10.1145/3466897
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HipaccVX: Wedding of OpenVX and DSL-based Code Generation
In: Journal of Real-Time Image Processing 18 (2021), S. 765 – 777
ISSN: 1861-8200
DOI: 10.1007/s11554-020-01015-5
URL: http://link.springer.com/article/10.1007/s11554-020-01015-5
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2020
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Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats
24th International Symposium on VLSI Design and Test (VDAT) (Bhubaneswar, 23. Juli 2020 – 25. Juli 2020)
In: Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT) 2020
DOI: 10.1109/VDAT50263.2020.9190305
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A Runtime System for Finite Element Methods in a Partitioned Global Address Space
ACM International Conference on Computing Frontiers 2020 (Catania, Sicily, Italy, 11. Mai 2020 – 13. Mai 2020)
In: Proceedings of the 17th ACM International Conference on Computing Frontiers (CF) 2020
DOI: 10.1145/3387902.3392628
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Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
2020
ISBN: 978-1-7281-7147-0
DOI: 10.1109/ASAP49362.2020
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Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs
International Workshop on Software and Compilers for Embedded Systems (SCOPES) (St. Goar, 25. Mai 2020 – 26. Mai 2020)
In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
DOI: 10.1145/3378678.3391878
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ExaStencils: Advanced multigrid solver generation
In: Hans-Joachim Bungartz, Severin Reiz, Benjamin Uekermann, Philipp Neumann, Wolfgang E. Nagel (Hrsg.): Lecture notes in computational science and engineering, Cham: Springer, 2020, S. 405-452 (Software for Exascale Computing SPPEXA 2016 – 2019, Bd.136)
ISBN: 978-3-030-47955-8
DOI: 10.1007/978-3-030-47956-5
URL: https://library.oapen.org/bitstream/handle/20.500.12657/41289/2020_Book_SoftwareForExascaleComputing-S.pdf?sequence=1#page=411
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ExaStencils – Advanced Multigrid Solver Generation
In: Hans-Joachim Bungartz, Severin Reiz, Philipp Neumann, Benjamin Uekermann, Wolfgang Nagel (Hrsg.): Software for Exascale Computing – SPPEXA 2016-2019, Springer, 2020, S. 405-452 (Lecture Notes in Computer Science and Engineering, Bd.136)
ISBN: 978-3-030-47955-8
DOI: 10.1007/978-3-030-47956-5_14
URL: https://www12.cs.fau.de/downloads/hannig/publications/ExaStencils_Advanced_Multigrid_Solver_Generation.pdf
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A Bibliometric Approach for Detecting the Gender Gap in Computer Science
In: Communications of the ACM 63 (2020), S. 39-45
ISSN: 0001-0782
DOI: 10.1145/3376901
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Unveiling Kernel Concurrency in Multiresolution Filters on GPUs with an Image Processing DSL
13th Workshop on General Purpose Processing Using GPU (GPGPU) (San Diego, CA, USA, 23. Februar 2020 – 23. Februar 2020)
In: Proceedings of the 13th Workshop on General Purpose Processing Using GPU (GPGPU) 2020
DOI: 10.1145/3366428.3380773
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Efficient Parallel Reduction on GPUs with Hipacc
23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 25. Mai 2020 – 26. Mai 2020)
In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
DOI: 10.1145/3378678.3391885
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The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL
57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. Juli 2020 – 23. Juli 2020)
In: Proceedings of the 57th Annual Design Automation Conference (DAC) 2020
DOI: 10.1109/DAC18072.2020.9218531
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Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks
(2020)
Open Access: https://arxiv.org/pdf/2008.09072
URL: https://arxiv.org/abs/2008.09072
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AnyHLS: High-Level Synthesis with Partial Evaluation
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Hamburg, 20. September 2020 – 25. September 2020)
DOI: 10.1109/tcad.2020.3012172
URL: https://arxiv.org/pdf/2002.05796.pdf
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AnyHLS: High-Level Synthesis with Partial Evaluation
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 (2020), S. 3202-3214
ISSN: 0278-0070
DOI: 10.1109/TCAD.2020.3012172
URL: https://arxiv.org/pdf/2002.05796.pdf
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2019
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Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic
ACM International Conference on Computing Frontiers 2019 (Alghero, Sardinia, 30. April 2019 – 2. Mai 2019)
DOI: 10.1145/3310273.3322833
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*-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing
In: Concurrency and Computation-Practice & Experience (2019)
ISSN: 1532-0626
DOI: 10.1002/cpe.5149
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DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs
ARCS 2019 – 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. Mai 2019 – 23. Mai 2019)
In: Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck (Hrsg.): Proceedings of the 32nd International Conference on Architecture of Computing Systems (ARCS) 2019
DOI: 10.1007/978-3-030-18656-2
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SYCL Code Generation for Multigrid Methods
22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES ’19) (Sankt Goar, Germany, 27. Mai 2019 – 29. Mai 2019)
In: 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES ’19) 2019
DOI: 10.1145/3323439.3323984
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Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays
In: Journal of Computers 14 (2019), S. 541-556
ISSN: 1796-203X
DOI: 10.17706/jcp.14.8.541-556
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Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards
In: Transactions on High-Performance Embedded Architectures and Compilers V, Springer, 2019, S. 1-20 (Lecture Notes in Computer Science (LNCS), Bd.11225)
ISBN: 978-3-662-58833-8
DOI: 10.1007/978-3-662-58834-5_1
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From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization
2019 International Symposium on Code Generation and Optimization (CGO) (Washington, DC, USA, 16. Februar 2019 – 20. Februar 2019)
In: Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO) 2019
DOI: 10.1109/CGO.2019.8661176
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ActorX10 and Run-Time Application Embedding
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 129-164 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_6
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Fundamentals
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 9-40 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_2
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Hybrid Network-on-Chip Simulation
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 77-99 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_4
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Introduction
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 1-7 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_1
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InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 41-76 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_3
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Modeling and Simulation of Invasive Applications and Architectures
Singapore: Springer, 2019
(Computer Architecture and Design Methodologies)
ISBN: 978-981-13-8386-1
DOI: 10.1007/978-981-13-8387-8
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Modeling and Simulation of Invasive Applications and Architectures Conclusions and Future Directions
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 165-168 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_7
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Parallel MPSoC Simulation and Architecture Evaluation
In: Sascha Roloff, Frank Hannig, Jürgen Teich (Hrsg.): Modeling and Simulation of Invasive Applications and Architectures, 2019, S. 101-128 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_5
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Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays
International Conference on Formal Methods and Models for System Design (MEMOCODE) (San Diego, 9. Oktober 2019 – 11. Oktober 2019)
In: Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE) 2019
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Synthesizing High-Performance Image Processing Applications with Hipacc
Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Florence, 25. März 2019 – 29. März 2019)
URL: https://www12.cs.fau.de/downloads/oezkan/publications/date-ubooth19.pdf
BibTeX: Download
(online publication)
2018
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Solving Maxwell’s Equations with Modern C++ and SYCL: A Case Study
The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Politecnico di Milano, Milan, 10. Juli 2018 – 12. Juli 2018)
In: Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
DOI: 10.1109/ASAP.2018.8445127
URL: https://www12.cs.fau.de/downloads/schmittch/publications/ASAGTFH18asap.pdf
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Special Issue on Heterogeneous Real-Time Image Processing
In: Journal of Real-Time Image Processing 14 (2018), S. 513-515
ISSN: 1861-8200
DOI: 10.1007/s11554-018-0763-2
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Embedded GPUs in Future Automated Cars
Design, Automation and Test in Europe (DATE) (Dresden, 19. März 2018 – 23. März 2018)
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(Working Paper) - , , , :
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs
4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Funchal, Madeira, Portugal, 16. März 2018 – 18. März 2018)
DOI: 10.5220/0006677302980306
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Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs
Design, Automation and Test in Europe (DATE) (Dresden, Germany, 19. März 2018 – 23. März 2018)
DOI: 10.23919/DATE.2018.8342050
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Path Planning for Highly Automated Driving on Embedded GPUs
4 (2018)
ISSN: 2079-9268
DOI: 10.3390/jlpea8040035
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OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Boulder, CO, USA, 29. April 2018 – 1. Mai 2018)
In: Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2018
DOI: 10.1109/FCCM.2018.00037
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The Gender Gap in Computer Science — A Bibliometric Analysis
(2018)
ISSN: 2191-5008
DOI: 10.25593/issn.2191-5008/CS-2018-02
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(Techreport) - , , , :
Automatic Kernel Fusion for Image Processing DSLs
21st International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 28. Mai 2018 – 30. Mai 2018)
In: Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2018
DOI: 10.1145/3207719.3207723
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Loop Parallelization Techniques for FPGA Accelerator Synthesis
In: Journal of Signal Processing Systems 90 (2018), S. 3-27
ISSN: 1939-8115
DOI: 10.1007/s11265-017-1229-7
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A Target Platform Description Language for Parallel Code Generation
31st GI/ITG International Conference on Architecture of Computing Systems (ARCS) (Braunschweig, 9. April 2018 – 12. April 2018)
In: Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS), Berlin: 2018
URL: https://www12.cs.fau.de/downloads/schmittch/publications/SHT18arcs.pdf
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Automating the Development of High-Performance Multigrid Solvers
In: Proceedings of the IEEE 106 (2018), S. 1969-1984
ISSN: 0018-9219
DOI: 10.1109/JPROC.2018.2854229
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Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution
In: Parallel Processing Letters 28 (2018), Art.Nr.: 1850016
ISSN: 0129-6264
DOI: 10.1142/S0129626418500160
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Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Milan, Italy, 10. Juli 2018 – 12. Juli 2018)
DOI: 10.1109/ASAP.2018.8445109
URL: https://ieeexplore.ieee.org/abstract/document/8445109/
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Symbolic Parallelization of Nested Loop Programs
Springer, 2018
ISBN: 978-3-319-73908-3
DOI: 10.1007/978-3-319-73909-0
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A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement
International Workshop on FPGAs for Software Programmers (Dublin, 31. August 2018)
In: Proceedings of the Fifth International Workshop on FPGAs for Software Programmers 2018
URL: https://www12.cs.fau.de/downloads/oezkan/publications/fsp18.pdf
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2017
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Efficiency in ILP Processing by Using Orthogonality
The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017) (Seattle, 10. Juli 2017 – 12. Juli 2017)
In: IEEE (Hrsg.): 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
DOI: 10.1109/ASAP.2017.7995282
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Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17) (Korea University, Seoul, Korea, 18. September 2017 – 20. September 2017)
In: 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip 2017
DOI: 10.1109/MCSoC.2017.17
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Environment Mapping Using Massively Parallel Architectures
Vehicle Intelligence (München, 5. Dezember 2017 – 7. Dezember 2017)
BibTeX: Download - , , , , :
Convoy Tracking for ADAS on Embedded GPUs
Intelligent Vehicles Symposium (IV 2017) (Redondo Beach, CA, USA, 11. Juni 2017 – 14. Juni 2017)
BibTeX: Download - :
Domain-specific and Resource-aware Computing (Habilitationsschrift, 2017)
DOI: 10.13140/RG.2.2.23418.13761
URL: https://www.cs12.tf.fau.de/files/2016/08/Frank_Hannig_Habilitation2017.pdf
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Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
In: IEEE Transactions on Computers 66 (2017), S. 488–501
ISSN: 0018-9340
DOI: 10.1109/TC.2016.2595560
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A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms
In: International Journal of Computational Science and Engineering 14 (2017), S. 150-163
ISSN: 1742-7185
DOI: 10.1504/IJCSE.2017.10003829
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Auto-vectorization for Image Processing DSLs
18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (Barcelona, 21. Juni 2017 – 22. Juni 2017)
In: Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) 2017
DOI: 10.1145/3078633.3081039
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Generating FPGA-based Image Processing Accelerators with Hipacc
International Conference on Computer Aided Design (ICCAD) (Irvine, 13. November 2017 – 16. November 2017)
In: Proceedings of the International Conference on Computer Aided Design (ICCAD) 2017
DOI: 10.1109/ICCAD.2017.8203894
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High Performance Network-on-Chip Simulation by Interval-based Timing Predictions
15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (Seoul, Republic of Korea, 15. Oktober 2017 – 20. Oktober 2017)
In: ACM (Hrsg.): Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2017
DOI: 10.1145/3139315.3139320
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TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays
Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 4. Dezember 2017 – 6. Dezember 2017)
DOI: 10.1109/RECONFIG.2017.8279818
URL: http://ieeexplore.ieee.org/document/8279818/
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A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays
International Conference on ReConFigurable Computing and FPGA’s (ReConFig) (Cancun, Mexico, 4. Dezember 2017 – 6. Dezember 2017)
DOI: 10.1109/RECONFIG.2017.8279768
URL: http://ieeexplore.ieee.org/document/8279768/
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Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
In: ACM Transactions on Embedded Computing Systems 17 (2017), S. 31:1-31:27
ISSN: 1539-9087
DOI: 10.1145/3092952
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Trends in Data Locality Abstractions for HPC Systems
In: IEEE Transactions on Parallel and Distributed Systems (2017)
ISSN: 1045-9219
DOI: 10.1109/TPDS.2017.2703149
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Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates
Symposium on Rapid System Prototyping (Seoul, South Korea, 19. Oktober 2017 – 20. Oktober 2017)
In: Proceedings of the Symposium on Rapid System Prototyping 2017
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A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
Fourth International Workshop on FPGAs for Software Programmers (FSP) (Ghent, 7. September 2017)
In: Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP) 2017
URL: https://ieeexplore.ieee.org/document/8084549
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Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Seattle, 10. Juli 2017 – 12. Juli 2017)
In: 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
DOI: 10.1109/ASAP.2017.7995273
URL: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf
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2016
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A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
In: Journal of Signal Processing Systems 89 (2016), S. 225-242
ISSN: 1939-8018
DOI: 10.1007/s11265-016-1187-5
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Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs
18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (Santa Cruz, CA, 7. Oktober 2016 – 8. Oktober 2016)
In: Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) 2016
DOI: 10.1109/HLDVT.2016.7748257
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A Quick Tour of High-Level Synthesis Solutions for FPGAs
In: Dirk Koch, Frank Hannig, and Daniel Ziener (Hrsg.): FPGAs for Software Programmers, Springer, 2016
DOI: 10.1007/978-3-319-26408-0_3
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Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings
Springer Verlag, 2016
ISBN: 9783319306940
DOI: 10.1007/978-3-319-30695-7
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Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS)
Berlin; Heidelberg: 2016
(Lecture Notes in Computer Science (LNCS), Bd. 9637)
ISBN: 978-3-319-30694-0
DOI: 10.1007/978-3-319-30695-7
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Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach
In: it – Information Technology 58 (2016), S. 297-307
ISSN: 1611-2776
DOI: 10.1515/itit-2016-0028
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Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, 18. Juni 2016 – 21. Juni 2016)
In: Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2016
DOI: 10.1109/SAMOS.2016.7818350
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FPGAs for Software Programmers
Berlin; Heidelberg: 2016
ISBN: 978-3-319-26406-6
DOI: 10.1007/978-3-319-26408-0
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FPGA versus Software Programming – Why, When, and How?
In: Dirk Koch, Frank Hannig, and Daniel Ziener (Hrsg.): FPGAs for Software Programmers, 2016, S. 1-21
DOI: 10.1007/978-3-319-26408-0_1
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HIPAcc: A Domain-Specific Language and Compiler for Image Processing
In: IEEE Transactions on Parallel and Distributed Systems 27 (2016), S. 210-224
ISSN: 1045-9219
DOI: 10.1109/TPDS.2015.2394802
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InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip
Design, Automation and Test in Europe (DATE) (Dresden, 14. März 2016 – 18. März 2016)
In: Tool presentation at the University Booth 2016
URL: https://www.date-conference.com/system/files/file/date16/ubooth/37912.pdf
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ActorX10: An Actor Library for X10
ACM SIGPLAN X10 Workshop (X10), ACM (Santa Barbara, CA)
In: Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) 2016
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HIPAcc
In: Dirk Koch, Frank Hannig, and Daniel Ziener (Hrsg.): FPGAs for Software Programmers, Springer, 2016
DOI: 10.1007/978-3-319-26408-0_12
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Big Data and HPC Acceleration with Vivado HLS
In: Dirk Koch, Frank Hannig, and Daniel Ziener (Hrsg.): FPGAs for Software Programmers, Springer, 2016, S. 115-136
DOI: 10.1007/978-3-319-26408-0_7
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Systems of Partial Differential Equations in ExaSlang
In: Software for Exascale Computing – SPPEXA 2013-2015, Berlin, Heidelberg, New York: Springer, 2016, S. 47-67 (Lecture Notes in Computational Science and Engineering, Bd.113)
ISBN: 9783319405261
DOI: 10.1007/978-3-319-40528-5_3
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LoopInvader: A Compiler for Tightly Coupled Processor Arrays
Design, Automation and Test in Europe (DATE) (Dresden, 14. März 2016 – 18. März 2016)
In: Tool presentation at the University Booth 2016
URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
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Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (London, 6. Juli 2016 – 8. Juli 2016)
In: Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016
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FPGA-Based Accelerator Design from a Domain-Specific Language
26th International Conference on Field-Programmable Logic and Applications (FPL) (Lausanne, 29. August 2016 – 2. September 2016)
In: Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL) 2016
DOI: 10.1109/FPL.2016.7577357
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2015
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Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms
48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (Pacific Grove, CA, 2. November 2014 – 5. November 2014)
In: Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) 2015
DOI: 10.1109/ACSSC.2014.7094471
BibTeX: Download - , , (Hrsg.):
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
2015
Open Access: http://arxiv.org/abs/1502.07241
URL: http://arxiv.org/abs/1502.07241
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Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures
In: Journal of Systems Architecture 61 (2015), S. 600
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.11.003
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Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
2015
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A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. Juni 2016 – 18. Juni 2015)
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
DOI: 10.1109/AHS.2015.7231157
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Resource-awareness on heterogeneous MPSoCs for image processing
In: Journal of Systems Architecture 61 (2015), S. 668-680
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.09.002
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Automatic Optimization of Hardware Accelerators for Image Processing
DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (Grenoble, 13. März 2015 – 13. März 2015)
In: Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) 2015
URL: http://arxiv.org/abs/1502.07448
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Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
In: Journal of Systems Architecture 61 (2015), S. 646-658
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.09.004
URL: https://www12.cs.fau.de/downloads/reiche/publications/RHRSHTF15.pdf
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Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 (San Francisco, CA, 7. Juni 2015 – 11. Juni 2015)
In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) 2015
DOI: 10.1145/2744769.2744840
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Invasive computing for predictable stream processing: A simulation-based case study
13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015 (Amsterdam, 8. Oktober 2015 – 9. Oktober 2015)
DOI: 10.1109/ESTIMedia.2015.7351761
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Loop Coarsening in C-based High-Level Synthesis
26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Toronto, 27. Juli 2015 – 29. Juli 2015)
In: Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
DOI: 10.1109/ASAP.2015.7245730
URL: https://www12.cs.fau.de/downloads/reiche/publications/SRHT15.pdf
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Generation of Multigrid-based Numerical Solvers for FPGA Accelerators
2nd International Workshop on High-Performance Stencil Computations (HiStencils) (Amsterdam, 20. Januar 2015 – 20. Januar 2015)
In: Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils) 2015
URL: https://www12.cs.fau.de/downloads/schmittch/publications/SSHTKK15histencils.pdf
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Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
International Embedded Systems Symposium (IESS) (Foz do Iguaçu, 3. November 2015 – 6. November 2015)
In: Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, and Achim Rettberg (Hrsg.): Proceedings of the International Embedded Systems Symposium (IESS) 2015
DOI: 10.1007/978-3-319-90023-0
URL: http://www.springer.com/us/book/9783319900223
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Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar, 1. Juni 2015 – 3. Juni 2015)
In: In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2015
DOI: 10.1145/2764967.2771933
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Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays
ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015 (Austin, 21. September 2015 – 23. September 2015)
In: Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2015
DOI: 10.1109/MEMCOD.2015.7340486
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On-demand fault-tolerant loop processing on massively parallel processor arrays
26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 (Toronto, 27. Juli 2015 – 29. Juli 2015)
In: In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
DOI: 10.1109/ASAP.2015.7245734
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Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays
In: Luk, Wayne, Constantinides, George A. (Hrsg.): Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015, S. 167-206
ISBN: 978-1-78326-696-8
DOI: 10.1142/9781783266975_0010
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Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing
11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 12. Juli 2015 – 18. Juli 2015)
In: Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) 2015
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2014
- , , :
Compact Code Generation for Tightly-Coupled Processor Arrays
In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 77(1-2) (2014), S. 5-29
ISSN: 1387-5485
DOI: 10.1007/s11265-014-0891-2
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Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays
DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES) (Dresden, Germany, 28. März 2014 – 28. März 2014)
URL: https://ecsi.org/resource/workshop/2014/3PMCES/DATE/paper/timing-analysis-heterogeneous-architecture-massively-parallel-processor-arrays
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Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror
In: Parallel Processing Letters 24 (2014)
ISSN: 0129-6264
DOI: 10.1142/S0129626414410011
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Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
2014
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Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach
In: ACM Transactions on Embedded Computing Systems 13 (2014), S. 133:1-133:29
ISSN: 1539-9087
DOI: 10.1145/2584660
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Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014)
2014
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Generating Highly Parallel Geometric Multigrid Solvers with the ExaStencils Apporach
3rd Workshop on Extreme-scale Programming Tools (New Orleans, 17. November 2014 – 17. November 2014)
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Massively Parallel Processor Architectures for Resource-aware Computing
First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing ) (Paderborn, 29. Mai 2014 – 30. Mai 2014)
In: Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) 2014
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ExaStencils: Advanced Stencil-Code Engineering – First Project Report
(2014)
Open Access: http://www.fim.uni-passau.de/fileadmin/files/forschung/mip-berichte/MIP1401.pdf
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ExaStencils: Advanced Stencil-Code Engineering
Euro-Par: Parallel Processing Workshops (Porto, 25. August 2014 – 26. August 2014)
In: Proceedings of Euro-Par 2014: Parallel Processing Workshops, Berlin; Heidelberg: 2014
DOI: 10.1007/978-3-319-14313-2_47
URL: http://link.springer.com/content/pdf/10.1007/978-3-319-14313-2_47.pdf
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Code Generation for Embedded Heterogeneous Architectures on Android
Conference on Design, Automation and Test in Europe (DATE) (Dresden, 24. März 2014 – 28. März 2014)
In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2014
DOI: 10.7873/DATE2014.099
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Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language
In: Journal of Parallel and Distributed Computing 74 (2014), S. 3191-3201
ISSN: 0743-7315
DOI: 10.1016/j.jpdc.2014.08.008
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Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 8. Oktober 2014 – 10. Oktober 2014)
In: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Gières, France: 2014
DOI: 10.1109/DASIP.2014.7115616
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Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (New Dehli, 12. Oktober 2014 – 17. Oktober 2014)
In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA: 2014
DOI: 10.1145/2656075.2656081
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Towards Actor-oriented Programming on PGAS-based Multicore Architectures
First International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Lübeck)
In: Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2014
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An Image Processing Library for C-based High-Level Synthesis
Field-Programmable Logic and Applications (FPL) (Munich, 1. September 2014 – 5. September 2014)
In: Proc. of Field-Programmable Logic and Applications (FPL), New York, NY, USA: 2014
DOI: 10.1109/FPL.2014.6927424
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High-Level Synthesis Revised – Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model
In: Parallel Computing: Accelerating Computational Science and Engineering (CSE), Amsterdam, The Netherlands: IOS Press, 2014, S. 497-506 (Advances in Parallel Computing, Bd.25)
ISBN: 978-1-61499-380-3
DOI: 10.3233/978-1-61499-381-0-497
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Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
First International Workshop on FPGAs for Software Programmers (FSP) (Munich, 1. September 2014 – 1. September 2014)
In: Proc. of the First International Workshop on FPGAs for Software Programmers (FSP) 2014
URL: http://arxiv.org/abs/1408.4721
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Domain-Specific Augmentations for High-Level Synthesis
25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Zurich, 18. Juni 2014 – 20. Juni 2014)
In: Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, NY, USA: 2014
DOI: 10.1109/ASAP.2014.6868653
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ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers
4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (New Orleans, LA, USA, 17. November 2014 – 17. November 2014)
In: Proc. of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), New York, NY, USA: 2014
DOI: 10.1109/WOLFHPC.2014.11
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An Evaluation of Domain-Specific Language Technologies for Code Generation
14th International Conference on Computational Science and its Applications (ICCSA) (Minho, Guimaraes, 30. Juni 2014 – 3. Juli 2014)
In: Proc. of the 14th International Conference on Computational Science and its Applications (ICCSA), New York, NY, USA: 2014
DOI: 10.1109/ICCSA.2014.16
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Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures
17th Euromicro Conference on Digital System Design, DSD 2014 (Verona, 27. August 2014 – 29. August 2014)
In: Proceedings of the EUROMICRO Digital System Design Conference (DSD) 2014
DOI: 10.1109/DSD.2014.105
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Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Dresden, 24. März 2014 – 28. Dezember 2017)
In: Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) 2014
Open Access: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
URL: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
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Symbolic inner loop parallelisation for massively parallel processor arrays
12th ACM/IEEE International Conference on Methods and Models for System Design, MEMOCODE 2014 (Lausanne, 19. Oktober 2014 – 21. Oktober 2014)
In: Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2014
DOI: 10.1109/MEMCOD.2014.6961865
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White Paper: Programming Abstractions for Data Locality
PADAL Workshop 2014 (Swiss National Supercomputing Center (CSCS), Lugano, Switzerland, 28. April 2014 – 29. April 2014)
In: Proc. of PADAL Workshop 2014
URL: http://www.padalworkshop.org/white-paper/
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Symbolic Mapping of Loop Programs onto Processor Arrays
In: Journal of Signal Processing Systems, Berlin; Heidelberg: Springer-Verlag, 2014, S. 31-59
DOI: 10.1007/s11265-014-0905-0
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2013
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Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. Juni 2013 – 7. Juni 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567544
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Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
Synopsys Users Group Conference (SNUG) (Munich, 14. Mai 2013 – 14. Mai 2013)
In: Proc. Synopsys Users Group Conference 2013
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System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures
ACM International Conference on Computing Frontiers (CF) (Ischia, 14. Mai 2013 – 16. Mai 2013)
In: Proc. ACM International Conference on Computing Frontiers, New York, NY, USA: 2013
DOI: 10.1145/2482767.2482770
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NoC Simulation in Heterogeneous Architectures for PGAS Programming Model
16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES) (St. Goar, 19. Juni 2013 – 21. Juni 2013)
In: Proc. 16th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2013
DOI: 10.1145/2463596.2463606
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Real-Time Range Image Preprocessing on FPGAs
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, 9. Dezember 2013 – 11. Dezember 2013)
In: Proc. International Conference on Reconfigurable Computing and FPGAs 2013
DOI: 10.1109/ReConFig.2013.6732325
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Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. Oktober 2013 – 10. Oktober 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
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A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. Oktober 2013 – 10. Oktober 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
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Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
In: Proc. 25th Workshop on Parallel Systems and Algorithms, Berlin, Germany: 2013
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Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing
International Conference on Parallel Computing (ParCo) (Munich, 10. September 2013 – 13. September 2013)
In: Proc. International Conference on Parallel Computing 2013
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Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. Juni 2013 – 7. Juni 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567543
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2012
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An Integrated Simulation Framework for Invasive Computing
Forum on Specification & Design Languages (FDL) (Vienna, 18. September 2012 – 20. September 2012)
In: Proc. of the Forum on Specification & Design Languages (FDL), New York, NY, USA: 2012
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Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays
In: ACM Transactions on Design Automation of Electronic Systems 18 (2012), S. 1-25
ISSN: 1084-4309
DOI: 10.1145/2390191.2390193
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Design of low power on-chip processor arrays
2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012 (Delft, 9. Juli 2012 – 11. Juli 2012)
In: Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2012
DOI: 10.1109/ASAP.2012.10
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Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging
11th International Symposium on Parallel and Distributed Computing (ISPDC) (Munich, 25. Juni 2012 – 29. Juni 2012)
In: Proc. of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), New York, NY, USA: 2012
DOI: 10.1109/ISPDC.2012.36
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Generating Device-specific GPU Code for Local Operators in Medical Imaging
26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) (Shanghai, 21. Mai 2012 – 25. Mai 2012)
In: Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), New York, NY, USA: 2012
DOI: 10.1109/IPDPS.2012.59
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Mastering Software Variant Explosion for GPU Accelerators
In: Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), Berlin; Heidelberg: Springer, 2012, S. 123-132 (Lecture Notes on Computer Science (LNCS))
DOI: 10.1007/978-3-642-36949-0_15
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Towards Domain-specific Computing for Stencil Codes in HPC
2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (Salt Lake City, UT, 10. November 2012 – 16. November 2012)
In: Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) 2012
DOI: 10.1109/SC.Companion.2012.136
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Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging
25th International Conference on Architecture of Computing Systems (ARCS) (Munich, 28. Februar 2012 – 2. März 2012)
In: Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), New York, NY, USA: 2012
DOI: 10.1007/978-3-642-28293-5_13
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A Prototype of an Invasive Tightly-Coupled Processor Array
2012 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Karlsruhe, 23. Oktober 2012 – 25. Oktober 2012)
In: Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), New York, NY, USA: 2012
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Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs
17th Asia and South Pacific Design Automation Conference (ASP-DAC) (Sydney, 30. Januar 2012 – 2. Februar 2012)
In: Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), New York, NY, USA: 2012
DOI: 10.1109/ASPDAC.2012.6164943
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Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation
15th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Schloss Rheinfels, St. Goar, 15. Mai 2012 – 16. Mai 2012)
In: Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), New York, NY, USA: 2012
DOI: 10.1145/2236576.2236582
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Simulation of Resource-Aware Applications on Heterogeneous Architectures
8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. Juli 2012 – 14. Juli 2012)
In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
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Power Management Strategies for Serial RapidIO Endpoints in FPGAs
IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (Toronto, 29. April 2012 – 1. Mai 2012)
In: Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), New York, NY, USA: 2012
DOI: 10.1109/FCCM.2012.26
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Symbolic loop parallelization of static control programs
8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. Juli 2012 – 14. Juli 2012)
In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
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2011
- , , , :
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays
2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig’11) (Cancun, 30. November 2011 – 2. Dezember 2011)
In: Proc. of ReConFig, New York, NY, USA: 2011
DOI: 10.1109/ReConFig.2011.91
URL: http://www.computer.org/portal/web/csdl/doi/10.1109/ReConFig.2011.91
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Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
New York, NY, USA: 2011
ISBN: 978-1-4577-1292-0
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Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10
14th International Workshop on Software and Compilers for Embedded Systems (St. Goar, 27. Juni 2011 – 28. Juni 2011)
In: Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2011
DOI: 10.1145/1988932.1988941
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Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays
In: IEEE Embedded Systems Letters 3 (2011), S. 58-61
ISSN: 1943-0663
DOI: 10.1109/LES.2011.2124438
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Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays
In: Journal of Low Power Electronics 7 (2011), S. 29-40
ISSN: 1546-1998
DOI: 10.1166/jolpe.2011.1114
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Towards Resource-Aware Programming on Intel’s Single-Chip Cloud Computer Processor
3rd Many-core Applications Research Community (MARC) Symposium (Ettlingen, 5. Juli 2011 – 6. Juli 2011)
In: Proceedings of the 3rd MARC Symposium, Karlsruhe, Germany: 2011
DOI: 10.5445/KSP/1000023937
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Distributed Resource Reservation in Massively Parallel Processor Arrays
25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS’11) (Anchorage, AK, 16. Mai 2011 – 20. Mai 2011)
In: Proc. of the 25th IEEE International Symposium on Parallel and Distributed Processing, New York, NY, USA: 2011
DOI: 10.1109/IPDPS.2011.157
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Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’11) (Santa Monica, CA, 11. September 2011 – 14. September 2011)
In: Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, New York, NY, USA: 2011
DOI: 10.1109/ASAP.2011.6043240
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Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration
9th IEEE Symposium on Application Specific Processors (SASP) (San Diego, CA, USA, 5. Juni 2011 – 6. Juni 2011)
In: Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP) 2011
DOI: 10.1109/SASP.2011.5941083
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Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration
24th International Conference on Architecture of Computing Systems (ARCS) (Lake Como, 24. Februar 2011 – 25. Februar 2011)
In: Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), Heidelberg: 2011
DOI: 10.1007/978-3-642-19137-4_6
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Detector Defect Correction of Medical Images on Graphics Processors
SPIE: Medical Imaging : Image Processing (Lake Buena Vista, Orlando, FL, 14. Februar 2011 – 16. Februar 2011)
In: Proceedings of the SPIE: Medical Imaging 2011: Image Processing 2011
DOI: 10.1117/12.877656
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2010
- , , , (Hrsg.):
Proc. 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors
New York, NY, USA: 2010
ISBN: 978-1-4244-6967-3
DOI: 10.1109/ASAP.2010.5540766
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Modeling and synthesis of communication subsystems for loop accelerator pipelines
21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. Juli 2010 – 9. Juli 2010)
In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
DOI: 10.1109/ASAP.2010.5540760
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A Deeply Pipelined and Parallel Architecture for Denoising Medical Images
IEEE International Conference on Field Programmable Technology (FPT’10) (Beijing, 8. Dezember 2010 – 10. Dezember 2010)
In: Proc. IEEE International Conference on Field Programmable Technology 2010
DOI: 10.1109/FPT.2010.5681464
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Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures
Embedded World Conference (Nuremberg, 3. März 2010 – 5. März 2010)
In: Proc. Embedded World Conference 2010
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Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect
Embedded World Conference (Nuremberg, 3. März 2010 – 5. März 2010)
In: Proceedings of the Embedded World Conference 2010
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Compilation Techniques for CGRAs: Exploring All Parallelization Approaches
International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS’10) (Scottsdale, AZ, 24. Oktober 2010 – 29. Oktober 2010)
In: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis 2010
DOI: 10.1145/1878961.1878995
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2009
- , , , :
FPGA Implementation of an Invasive Computing Architecture
IEEE International Conference on Field Programmable Technology (FPT) (Sydney, 9. Dezember 2009 – 11. Dezember 2009)
In: Proceedings of the IEEE International Conference on Field Programmable Technology 2009
DOI: 10.1109/FPT.2009.5377633
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FSM-Controlled Architectures for Linear Invasion
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (Florianópolis)
In: Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration 2009
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Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. März 2009 – 13. März 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_23
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A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors
In: Microprocessors and Microsystems 33 (2009), S. 53-62
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2008.08.007
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Impact of loop tiling on the controller logic of acceleration engines
2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009 (Boston, MA, 7. Juli 2009 – 9. Juli 2009)
In: Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2009
DOI: 10.1109/ASAP.2009.21
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Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines
20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Boston, MA, 7. Juli 2009 – 9. Juli 2009)
In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors 2009
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Scheduling Techniques for High-Throughput Loop Accelerators (Dissertation, 2009)
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Parallelization Approaches for Hardware Accelerators – Loop Unrolling versus Loop Partitioning
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. März 2009 – 13. März 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_5
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Model-based synthesis and optimization of static multi-rate image processing algorithms
2009 Design, Automation and Test in Europe Conference and Exhibition, DATE ’09 (Nice, 20. April 2009 – 24. April 2009)
In: Proceedings of Design, Automation and Test in Europe (DATE 2009) 2009
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=70350072695&origin=inward
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Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures
In: Journal of Low Power Electronics 5 (2009), S. 96-105
ISSN: 1546-1998
DOI: 10.1166/jolpe.2009.1008
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System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance
4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC) (Vienna, 22. September 2009 – 25. September 2009)
In: Proceedings of the 4th International Symposium on Embedded Multicore Systems-on-Chip 2009
DOI: 10.1109/ICPPW.2009.72
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Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop) (Island of Samos, 20. Juli 2009 – 23. Juli 2009)
In: Proceedings of the 9th International Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS), Berlin / Heidelberg: 2009
DOI: 10.1007/978-3-642-03138-0_31
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Optimization Flow for Algorithm Mapping on Graphics Cards
Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) (Barcelona, 12. Juli 2009 – 18. Juli 2009)
In: Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems 2009
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Acceleration of multiresolution imaging algorithms: A comparative study
2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009 (Boston, MA, 7. Juli 2009 – 9. Juli 2009)
In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2009
DOI: 10.1109/ASAP.2009.8
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2008
- Dutta Hritam, Hannig Frank, Hartl Matthias, Kissler Dmitrij, Teich Jürgen:
Domain-Specific Reconfigurable MPSoC-Systems – Challenges and Trends
Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe (Munich, Germany)
In: Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe, New York: 2008
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Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices
2nd HiPEAC Workshop on Reconfigurable Computing (Gothenburg)
In: Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing 2008
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PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Fourth International Workshop on Applied Reconfigurable Computing (ARC) (London, 26. März 2008 – 28. März 2008)
In: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, Berlin Heidelberg: 2008
DOI: 10.1007/978-3-540-78610-8_30
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The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications
GI/ITG/GMM-Workshop — Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Freiburg, 3. März 2008 – 5. März 2008)
In: Proceedings of the GI/ITG/GMM-Workshop — Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2008
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Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (Lisbon, 10. September 2008 – 12. September 2008)
In: Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2008
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MAML: An ADL for Designing Single and Multiprocessor Architectures
In: Prabhat Mishra and Nikil Dutt (Hrsg.): Processor Description Languages, Elsevier Inc., 2008, S. 295-327 (Systems on Silicon Series)
ISBN: 9780123742872
DOI: 10.1016/B978-012374287-2.50015-X
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Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 – 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.24
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Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures
International Conference on Field Programmable Logic and Applications (FPL) (Heidelberg, 8. September 2008 – 10. September 2008)
In: Proceedings of the International Conference on Field Programmable Logic and Applications, New York: 2008
DOI: 10.1109/FPL.2008.4629969
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Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 – 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.1
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Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (Palo Alto, CA, 14. April 2008 – 15. April 2008)
In: Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines 2008
DOI: 10.1109/FCCM.2008.16
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2007
- , , , , , , , , :
Massively Parallel Processor Architectures: A Co-design Approach
3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) (Montpellier, 18. Juni 2007 – 20. Juni 2007)
In: Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) 2007
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Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays
In: Journal of Systems Architecture 53 (2007), S. 300-309
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2006.10.009
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Schwach-programmiert macht stark
In: Design & Elektronik (2007), S. 34-39
ISSN: 0933-8667
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Modeling of interconnection networks in massively parallel processor architectures
20th International Conference on Architecture of Computing Systems, ARCS 2007 (Zurich, 12. März 2007 – 15. März 2007)
In: Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007) 2007
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=37249015485&origin=inward
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Efficient event-driven simulation of parallel processor architectures
10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007 (Nice)
In: Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2007
DOI: 10.1145/1269843.1269854
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A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, 25. Juni 2007 – 28. Juni 2007)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 2007
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2006
- , , , , :
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Steamboat Springs, CO, 11. September 2006 – 13. September 2006)
In: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors 2006
DOI: 10.1109/ASAP.2006.4
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A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms
In: Technical Report 04-2006, 2006
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Controller Synthesis for Mapping Partitioned Programs on Array Architectures
19th International Conference on Architecture of Computing Systems (ARCS) (Frankfurt am Main, 13. März 2006 – 16. März 2006)
In: Proceedings of the 19th International Conference on Architecture of Computing Systems, Berlin, Heidelberg, New York: 2006
DOI: 10.1007/11682127_13
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Hierarchical Partitioning for Piecewise Linear Algorithms
5th International Conference on Parallel Computing in Electrical Engineering (PARELEC) (Bialystok, 13. September 2006 – 17. September 2006)
In: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering 2006
DOI: 10.1109/PARELEC.2006.43
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Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology
In: International Journal of Embedded Systems 2 (2006), S. 114-127
ISSN: 1741-1068
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Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints
6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing (Paderborn, 17. Januar 2006 – 18. Januar 2006)
In: Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, Paderborn, Germany: 2006
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Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays — Architectural Parameters and Methodology
In: International Journal of Embedded Systems 2 (2006), S. 114-127
ISSN: 1741-1068
DOI: 10.1504/IJES.2006.010170
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Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays
18th International Conference on Parallel and Distributed Computing and Systems (PDCS) (Dallas, TX, 13. November 2006 – 15. November 2006)
In: Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems 2006
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A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template
2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) (, 3. Juli 2006 – 5. Juli 2006)
In: Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) 2006
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Hardware cost analysis for weakly programmable processor arrays
2006 International Symposium on System-on-Chip, SOC (Tampere, 14. November 2006 – 16. November 2006)
In: Proceedings of the International Symposium on System-on-Chip (SoC) 2006
DOI: 10.1109/ISSOC.2006.321996
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A Generic Framework for Rapid Prototyping of System-on-Chip Designs
International Conference on Computer Design (CDES) (Las Vegas, NV)
In: Proceedings of the International Conference on Computer Design (CDES) 2006
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A highly parameterizable parallel processor array architecture
2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (Bangkok, 13. Dezember 2006 – 15. Dezember 2006)
In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006) 2006
DOI: 10.1109/FPT.2006.270293
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MAML – An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I
In: Technical Report 03-2006, 2006
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Modeling of Interconnection Networks in Massively Parallel Processor Architectures
In: Technical Report 05-2006, 2006
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(Techreport) - , , , , , :
An Architecture Description Language for Massively Parallel Processor Architectures
9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Dresden, 20. Februar 2006 – 22. Februar 2006)
In: Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2006
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2005
- , , , , , , :
Defragmenting the Module Layout of a Partially Reconfigurable Device
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. Juni 2005 – 30. Juni 2005)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
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Co-Design of Massively Parallel Embedded Processor Architectures
First ReCoSoC Workshop (Montpellier)
In: Proceedings of the first ReCoSoC Workshop 2005
BibTeX: Download - Dutta Hritam, Hannig Frank, Ruckdeschel Holger, Teich Jürgen:
Automatic FIR Filter Generation for FPGAs
Embedded Computer Systems: Architectures, Modeling, and Simulation. (Island of Samos, 18. Juli 2005 – 20. Juli 2005)
In: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), Berlin, Heidelberg, New York: 2005
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Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures
In: Technical Report 03-2005, 2005
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Output Serialization for FPGA-based and Coarse-grained Processor Arrays
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. Juni 2005 – 30. Juni 2005)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
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Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems
IEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005 (Samos)
In: Proceedings of Application-specific Systems, Architectures and Processors (ASAP) 2005
DOI: 10.1109/ASAP.2005.64
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2004
- , , :
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays — Constraints and Methodology
18th International Parallel and Distributed Processing Symposium (IPDPS 2004), (Santa Fe, NM, 26. April 2004 – 30. April 2004)
In: Proceedings of the 18th International Parallel and Distributed Processing Symposium 2004
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Regular Mapping for Coarse-grained Reconfigurable Architectures
IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ) (Montreal, Quebec, 17. Mai 2004 – 21. Mai 2004)
In: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing 2004
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Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) (Washington, DC)
In: Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) 2004
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Dynamic Piecewise Linear/Regular Algorithms
Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ) (Dresden, 7. September 2004 – 10. September 2004)
In: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) 2004
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Energy Estimation and Optimization for Piecewise Regular Processor Arrays
In: Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, New York, U.S.A.,: Marcel Dekker, 2004, S. 107-126 (Signal Processing and Communication)
ISBN: 0-8247-4711-9
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Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP ) (Galveston, TX, 27. September 2004 – 29. September 2004)
In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2004) 2004
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Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms
In: Technical Report 01-2004, 2004
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High-speed event-driven RTL compiled simulation
International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS’04) (Samos, 19. Juli 2004 – 21. Juli 2004)
In: Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS’04) 2004
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=35048851603&origin=inward
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2002
- , :
Energy Estimation for Piecewise Regular Processor Arrays
Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), (Island of Samos, 22. Juli 2002 – 25. Juli 2002)
In: Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation 2002
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Energy Estimation of Nested Loop Programs
14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), (Winnipeg, Manitoba, 10. August 2002 – 13. August 2002)
In: Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures 2002
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Generation of Distributed Loop Control
In: E. Deprettere, J. Teich, and S. Vassiliadis (Hrsg.): Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), Berlin, Germany: Springer, 2002, S. 154-170
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2001
- , , :
Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays
35th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA)
In: Matthews M.B. (Hrsg.): Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers 2001
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0035573058&origin=inward
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Design Space Exploration for Massively Parallel Processor Arrays
Sixth International Conference on Parallel Computing Technologies (PaCT-2001) (Novosibirsk, 3. September 2001 – 7. September 2001)
In: Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001) 2001
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