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Architecture and Compiler Design

Bereichsnavigation: Forschung
  • Arbeitsgruppen
    • Approximate Computing
    • Architecture and Compiler Design
    • Effiziente Algorithmen und Kombinatorische Optimierung
    • Reconfigurable Computing
    • System-level Design Automation
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Architecture and Compiler Design

Kontakt

PD Dr.-Ing. Frank Hannig

  • Telefon: +49 9131 85-25153
  • E-Mail: frank.hannig@fau.de

Prof. Dr.-Ing. Jürgen Teich

  • Telefon: +49 9131 85-25150
  • E-Mail: juergen.teich@fau.de

Die Arbeitsgruppe Architecture and Compiler Design (ACD) betrachtet den ganzheitlichen Entwurf von Rechensystemen. Dies umfasst folgende Forschungsfelder: Entwicklungswerkzeuge zur Modellierung, Simulation und Generierung von hochparallelen Architekturen wie z. B. dedizierte Akzeleratoren, eng gekoppelte Prozessorfelder bis hin zu heterogenen MPSoCs (Multi-Processor System-on-Chip), sowie Methoden und Compiler zur Abbildung von Algorithmen auf diese.

Einen weiteren Forschungsschwerpunkt bildet das Gebiet des domänenspezifischen Rechnens. Einerseits erforschen wir hier domänenspezifische Sprachen, die für ein bestimmtes Anwendungsgebiet (z. B. medizinische Bildverarbeitung, Fahrerassistenzsysteme oder Numerik im Höchstleistungsrechnern (HPC)) zugeschnitten sind, somit die Produktivität bei der Entwicklung steigern können und gleichzeitig Programmiererinnen oder Programmierer von Parallelisierungs- oder Architekturdetails auf unterster Ebene abschirmen. Andererseits entwickeln wir zugehörige optimierende Compiler und Generatoren, die aus ein und demselben Programm für ein einzigartig breites Spektrum an Prozessoren, wie z. B. moderne Mehrkernprozessoren mit Vektoreinheiten, Grafikprozessoren (GPUs), FPGAs bis hin zu MPSoCs, wie sie in Smart Phones und Tablet-PCs Verwendung finden, effizienten Code erzeugen können.

Aktuell laufende Projekte

  • Dedizierte massiv parallele Systeme – Details
  • DI-EDAI
  • MAP
  • NA³Os
  • OpTC
  • InvasIC: Sonderforschungsbereich/Transregio 89 — Invasives Rechnen
    • Grundlagen Invasiven Rechnens (A01)
    • Charakterisierung und Analyse Invasiver Algorithmen zur Entwurfszeit (A04)
    • Invasive eng gekoppelte Prozessorfelder (B02)
    • Übersetzung und Code-Erzeugung für Invasive Programme (C03)
    • TCPA_INT – Integration und Verbindung von eng gekoppelten Prozessorfeldern (T01)
    • Zentrale Dienste des SFB/Transregio und Öffentlichkeitsarbeit (Z01)
    • Validierung und Demonstrator (Z02)

Open Source Projekte

  • HIPAcc
  • ml-lib

Abgeschlossene Projekte

  • BUILDABONG – Entwurf anwendungsspezifischer Prozessoren
  • CoMap
  • EVOLIVO
  • ExaStencils
  • Fit4ML
  • HBS: Graduiertenkolleg „Heterogene Bildsysteme“, Projekt B3
  • HighPerMeshes
  • INI.FAU: Parallelisierung und Ressourcenabschätzung von Algorithmen für heterogene FAS-Architekturen
  • MMSys
  • InvasIC: Sonderforschungsbereich/Transregio 89 — Invasives Rechnen
    • Simulation invasiver Anwendungen und invasiver Architekturen (C02)
    • Simulative Entwurfsraumexploration (C02)
  • KISS

Publikationen


  • Sousa É., Witterauf M., Brand M., Tanase AP., Hannig F., Teich J.:
    Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
    29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Milan, Italy, 10. Juli 2018 - 12. Juli 2018)
    DOI: 10.1109/ASAP.2018.8445109
    URL: https://ieeexplore.ieee.org/abstract/document/8445109/
    BibTeX: Download
  • Mattauch S., Lohmann K., Hannig F., Lohmann D., Teich J.:
    The Gender Gap in Computer Science --- A Bibliometric Analysis
    (2018)
    ISSN: 2191-5008
    DOI: 10.25593/issn.2191-5008/CS-2018-02
    BibTeX: Download
  • Hannig F., Herkersdorf A.:
    Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures
    In: Journal of Systems Architecture 61 (2015), S. 600
    ISSN: 1383-7621
    DOI: 10.1016/j.sysarc.2015.11.003
    BibTeX: Download
  • Paul J., Stechele W., Oechslein B., Erhardt C., Schedel J., Lohmann D., Schröder-Preikschat W., Kröhnert M., Asfour T., Sousa É., Hannig F., Lari V., Teich J., Grudnitsky A., Bauer L., Henkel J.:
    Resource-awareness on heterogeneous MPSoCs for image processing
    In: Journal of Systems Architecture 61 (2015), S. 668-680
    ISSN: 1383-7621
    DOI: 10.1016/j.sysarc.2015.09.002
    BibTeX: Download
  • Paul J., Stechele W., Sousa É., Lari V., Hannig F., Teich J., Kröhnert M., Asfour T.:
    Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
    2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 8. Oktober 2014 - 10. Oktober 2014)
    In: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Gières, France: 2014
    DOI: 10.1109/DASIP.2014.7115616
    BibTeX: Download
  • Roloff S., Hannig F., Teich J.:
    High Performance Network-on-Chip Simulation by Interval-based Timing Predictions
    15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (Seoul, Republic of Korea, 15. Oktober 2017 - 20. Oktober 2017)
    In: ACM (Hrsg.): Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2017
    DOI: 10.1145/3139315.3139320
    BibTeX: Download
  • Witterauf M., Hannig F., Teich J.:
    Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates
    Symposium on Rapid System Prototyping (Seoul, South Korea, 19. Oktober 2017 - 20. Oktober 2017)
    In: Proceedings of the Symposium on Rapid System Prototyping 2017
    BibTeX: Download
  • Roloff S., Pöppl A., Schwarzer T., Wildermann S., Baader M., Glaß M., Hannig F., Teich J.:
    ActorX10: An Actor Library for X10
    ACM SIGPLAN X10 Workshop (X10), ACM (Santa Barbara, CA)
    In: Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) 2016
    BibTeX: Download
  • Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
    LoopInvader: A Compiler for Tightly Coupled Processor Arrays
    Design, Automation and Test in Europe (DATE) (Dresden, 14. März 2016 - 18. März 2016)
    In: Tool presentation at the University Booth 2016
    URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
    BibTeX: Download
  • Roloff S., Hannig F., Teich J.:
    InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip
    Design, Automation and Test in Europe (DATE) (Dresden, 14. März 2016 - 18. März 2016)
    In: Tool presentation at the University Booth 2016
    URL: https://www.date-conference.com/system/files/file/date16/ubooth/37912.pdf
    BibTeX: Download
  • Roloff S., Wildermann S., Hannig F., Teich J.:
    Invasive computing for predictable stream processing: A simulation-based case study
    13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015 (Amsterdam, 8. Oktober 2015 - 9. Oktober 2015)
    DOI: 10.1109/ESTIMedia.2015.7351761
    BibTeX: Download
  • Tanase AP., Witterauf M., Teich J., Hannig F., Lari V.:
    On-demand fault-tolerant loop processing on massively parallel processor arrays
    26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 (Toronto, 27. Juli 2015 - 29. Juli 2015)
    In: In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
    DOI: 10.1109/ASAP.2015.7245734
    BibTeX: Download
  • Lari V., Tanase AP., Teich J., Witterauf M., Khosravi F., Hannig F., Meyer B.:
    A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays
    NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. Juni 2016 - 18. Juni 2015)
    In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
    DOI: 10.1109/AHS.2015.7231157
    BibTeX: Download
  • Roloff S., Schafhauser D., Hannig F., Teich J.:
    Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
    52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 (San Francisco, CA, 7. Juni 2015 - 11. Juni 2015)
    In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) 2015
    DOI: 10.1145/2744769.2744840
    BibTeX: Download
  • Afzal A., Schmitt C., Alhaddad S., Grynko Y., Teich J., Förstner J., Hannig F.:
    Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study
    The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Politecnico di Milano, Milan, 10. Juli 2018 - 12. Juli 2018)
    In: Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
    DOI: 10.1109/ASAP.2018.8445127
    URL: https://www12.cs.fau.de/downloads/schmittch/publications/ASAGTFH18asap.pdf
    BibTeX: Download
  • Kenter T., Mahale G., Alhaddad S., Grynko Y., Schmitt C., Afzal A., Hannig F., Förstner J., Plessl C.:
    OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
    The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Boulder, CO, USA, 29. April 2018 - 1. Mai 2018)
    In: Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2018
    DOI: 10.1109/FCCM.2018.00037
    BibTeX: Download
  • Reiche O., Özkan MA., Membarth R., Teich J., Hannig F.:
    Generating FPGA-based Image Processing Accelerators with Hipacc
    International Conference on Computer Aided Design (ICCAD) (Irvine, 13. November 2017 - 16. November 2017)
    In: Proceedings of the International Conference on Computer Aided Design (ICCAD) 2017
    DOI: 10.1109/ICCAD.2017.8203894
    BibTeX: Download
  • Özkan MA., Reiche O., Hannig F., Teich J.:
    A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
    Fourth International Workshop on FPGAs for Software Programmers (FSP) (Ghent, 7. September 2017)
    In: Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP) 2017
    URL: https://ieeexplore.ieee.org/document/8084549
    BibTeX: Download
  • Reiche O., Kobylko C., Hannig F., Teich J.:
    Auto-vectorization for Image Processing DSLs
    18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (Barcelona, 21. Juni 2017 - 22. Juni 2017)
    In: Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) 2017
    DOI: 10.1145/3078633.3081039
    BibTeX: Download
  • Özkan MA., Reiche O., Hannig F., Teich J.:
    Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
    28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Seattle, 10. Juli 2017 - 12. Juli 2017)
    In: 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
    DOI: 10.1109/ASAP.2017.7995273
    URL: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf
    BibTeX: Download
  • Qiao B., Reiche O., Hannig F., Teich J.:
    Automatic Kernel Fusion for Image Processing DSLs
    21st International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 28. Mai 2018 - 30. Mai 2018)
    In: Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2018
    DOI: 10.1145/3207719.3207723
    BibTeX: Download
  • Reiche O., Özkan MA., Hannig F., Teich J., Schmid M.:
    Loop Parallelization Techniques for FPGA Accelerator Synthesis
    In: Journal of Signal Processing Systems 90 (2018), S. 3-27
    ISSN: 1939-8115
    DOI: 10.1007/s11265-017-1229-7
    BibTeX: Download
  • Fickenscher J., Schlumberger J., Hannig F., Bouzouraa ME., Teich J.:
    Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs
    Design, Automation and Test in Europe (DATE) (Dresden, Germany, 19. März 2018 - 23. März 2018)
    DOI: 10.23919/DATE.2018.8342050
    BibTeX: Download
  • Fickenscher J., Hannig F., Teich J., Bouzouraa ME.:
    Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs
    4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Funchal, Madeira, Portugal, 16. März 2018 - 18. März 2018)
    DOI: 10.5220/0006677302980306
    BibTeX: Download
  • Fickenscher J., Hannig F., Bouzouraa ME., Teich J.:
    Embedded GPUs in Future Automated Cars
    Design, Automation and Test in Europe (DATE) (Dresden, 19. März 2018 - 23. März 2018)
    BibTeX: Download
  • Fickenscher J., Bouzouraa ME., Hannig F., Teich J.:
    Environment Mapping Using Massively Parallel Architectures
    Vehicle Intelligence (München, 5. Dezember 2017 - 7. Dezember 2017)
    BibTeX: Download
  • Fickenscher J., Reinhart S., Bouzouraa ME., Hannig F., Teich J.:
    Convoy Tracking for ADAS on Embedded GPUs
    Intelligent Vehicles Symposium (IV 2017) (Redondo Beach, CA, USA, 11. Juni 2017 - 14. Juni 2017)
    BibTeX: Download
  • Fickenscher J., Reiche O., Schlumberger J., Hannig F., Teich J.:
    Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs
    18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (Santa Cruz, CA, 7. Oktober 2016 - 8. Oktober 2016)
    In: Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) 2016
    DOI: 10.1109/HLDVT.2016.7748257
    BibTeX: Download
  • Tanase AP., Witterauf M., Teich J., Hannig F.:
    Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
    In: ACM Transactions on Embedded Computing Systems 17 (2017), S. 31:1-31:27
    ISSN: 1539-9087
    DOI: 10.1145/3092952
    BibTeX: Download
  • Unat D., Dubey A., Hoefler T., Shalf J., Abraham M., Bianco M., Chamberlain BL., Cledat R., Edwards HC., Finkel H., Fürlinger K., Hannig F., Jeannot E., Kamil A., Keasler J., Kelly PHJ., Leung VJ., Ltaief H., Maruyama N., Newburn C., Pericàs M.:
    Trends in Data Locality Abstractions for HPC Systems
    In: IEEE Transactions on Parallel and Distributed Systems (2017)
    ISSN: 1045-9219
    DOI: 10.1109/TPDS.2017.2703149
    BibTeX: Download
  • Brand M., Hannig F., Tanase AP., Teich J.:
    Efficiency in ILP Processing by Using Orthogonality
    The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017) (Seattle, 10. Juli 2017 - 12. Juli 2017)
    In: IEEE (Hrsg.): 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
    DOI: 10.1109/ASAP.2017.7995282
    BibTeX: Download
  • Brand M., Hannig F., Tanase AP., Teich J.:
    Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
    IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17) (Korea University, Seoul, Korea, 18. September 2017 - 20. September 2017)
    In: 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip 2017
    DOI: 10.1109/MCSoC.2017.17
    BibTeX: Download
  • Sousa É., Tanase AP., Hannig F., Teich J.:
    A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays
    International Conference on ReConFigurable Computing and FPGA's (ReConFig) (Cancun, Mexico, 4. Dezember 2017 - 6. Dezember 2017)
    DOI: 10.1109/RECONFIG.2017.8279768
    URL: http://ieeexplore.ieee.org/document/8279768/
    BibTeX: Download
  • Sousa É., Chakraborty A., Tanase AP., Hannig F., Teich J.:
    TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays
    Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 4. Dezember 2017 - 6. Dezember 2017)
    DOI: 10.1109/RECONFIG.2017.8279818
    URL: http://ieeexplore.ieee.org/document/8279818/
    BibTeX: Download
  • Khdr H., Pagani S., Rodrigues Sousa E., Lari V., Pathania A., Hannig F., Shafique M., Teich J., Henkel J.:
    Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
    In: IEEE Transactions on Computers 66 (2017), S. 488--501
    ISSN: 0018-9340
    DOI: 10.1109/TC.2016.2595560
    BibTeX: Download
  • Fickenscher J., Hannig F., Teich J.:
    DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs
    ARCS 2019 - 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. Mai 2019 - 23. Mai 2019)
    In: Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck (Hrsg.): Proceedings of the 32nd International Conference on Architecture of Computing Systems (ARCS) 2019
    DOI: 10.1007/978-3-030-18656-2
    BibTeX: Download
  • Fickenscher J., Schmidt S., Hannig F., Bouzouraa ME., Teich J.:
    Path Planning for Highly Automated Driving on Embedded GPUs
    4 (2018)
    ISSN: 2079-9268
    DOI: 10.3390/jlpea8040035
    BibTeX: Download
  • Groth S., Schmitt C., Teich J., Hannig F.:
    SYCL Code Generation for Multigrid Methods
    22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) (Sankt Goar, Germany, 27. Mai 2019 - 29. Mai 2019)
    In: 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) 2019
    DOI: 10.1145/3323439.3323984
    BibTeX: Download
  • Fickenscher J.:
    Performance Modeling and Parallelization of Environment Perception and Path Planning Algorithms for Heterogeneous Advanced Driver Assistance System Architectures (Dissertation, 2020)
    BibTeX: Download
  • Plagwitz P., Hannig F., Teich J.:
    TRAC: Compilation-based Design of Transformer Accelerators for FPGAs
    International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
    In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
    DOI: 10.1109/FPL57034.2022.00015
    BibTeX: Download
  • Sabih M., Hannig F., Teich J.:
    DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks
    2nd European Workshop on Machine Learning and Systems (EuroMLSys) (Rennes, France, 5. April 2022 - 8. April 2022)
    In: Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys), New York, NY, United States: 2022
    DOI: 10.1145/3517207.3526982
    BibTeX: Download
  • Brand M., Keszöcze O., Teich J.:
    Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview
    In: IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2022), S. 2661 - 2666
    ISSN: 1057-7130
    DOI: 10.1109/TCSII.2022.3173753
    BibTeX: Download
  • Heidorn C., Meyerhöfer N., Schinabeck C., Hannig F., Teich J.:
    Hardware-Aware Evolutionary Filter Pruning
    International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. Juli 2022 - 7. Juli 2022)
    DOI: 10.1007/978-3-031-15074-6_18
    BibTeX: Download
  • Brand M.:
    Approximate and Reconfigurable Precision Instruction Set Processors for Tightly Coupled Processor Arrays (Dissertation, 2024)
    DOI: 10.25593/open-fau-601
    URL: https://open.fau.de/handle/openfau/31038
    BibTeX: Download
  • Sabih M., Karim A., Wittmann J., Hannig F., Teich J.:
    Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
    International Conference on Field Programmable Technology (FPT 2024) (Sydney, Australia, 10. Dezember 2024 - 12. Dezember 2024)
    BibTeX: Download
  • Tahoori MB., Becker J., Henkel J., Kunz W., Schlichtmann U., Sigl G., Teich J., Wehn N.:
    Multi-Partner Project: Open-source Design Tools for Co-development of AI Algorithms and AI Chips
    Design, Automation and Test in Europe Conference 2025 (Lyon, 31. März 2025 - 2. April 2025)
    BibTeX: Download

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