V2 + Ü2 (combined 5 ECTS) + optional P2 (FPGA & VHDL Labs, 2.5 ECTS),
Computer Science, IuK, SIM, Medical and Health Engineering, Mechatronics, and Computational Engineering
Lecture, location, and time:
Thursday, 16:15 – 17:45 hrs. Room 01.255-128
Registration on StudOn
The first lecture will take place on Thursday 21.10.2021 at 16:15 hrs. FAU’s 3G rule applies.
Exercises, location and time:
Thursday, 14:15 – 15:45 hrs. Room 02.134-113
The first exercise will take place on Thursday 4.11.2021 at 14:15 hrs.
Lab, location, and time:
The first lab will take place on Friday 05.11.2021 at 14:15 hrs.
Course (slides, exercises, other files):
All important documents can be found in StudOn
Reconfigurable (adaptive) computing is a novel yet important research field investigating the capability of hardware to adapt to changing computational requirements such as emerging standards, late design changes, and even to changing processing requirements arising at run-time. Reconfigurable computing thus benefits from a) the programmability of software similar to the Von Neumann computer and b) the speed and efficiency of parallel hardware execution.
The purpose of the course reconfigurable computing is to instruct students about the possibilities and rapidly growing interest in adaptive hardware and corresponding design techniques by providing them the necessary knowledge for understanding and designing reconfigurable hardware systems and studying applications benefiting from dynamic hardware reconfiguration.
After a general introduction about the benefits and application ranges of reconfigurable (adaptive) computing in contrast to general-purpose and application-specific computing, the following topics will be covered:
- Reconfigurable computing systems: Introduction of available technology including fine-grained look-up table (LUT-) based reconfigurable systems such as field-programmable gate arrays (FPGA) as well as newest coarse-grained architectures and technology.
- Design and implementation: Algorithms and steps (design entry, functional simulation, logic synthesis, technology mapping, place and route, bitstream generation) to implement (map) algorithms to FPGAs. The main focus lies on logic synthesis algorithms for FPGAs, in particular, LUT technology mapping.
- Temporal partitioning: techniques to reconfigure systems over time. Covered are the problems of mapping large circuits which do not fit one single device. Several temporal partitioning techniques are studied and compared.
- Temporal placement: Techniques and algorithms to exploit the possibility of partial and dynamic (run-time) hardware reconfiguration. Here, OS-like services are needed that optimize the allocation and scheduling of modules at run-time.
- Online communication: Modules dynamically placed at run-time on a given device need to communicate as well as transport data off-chip. State-of-the-art techniques are introduced how modules can communicate data at run-time including bus-oriented as well as network-on-a-chip (NoC) approaches.
- Designing reconfigurable applications on Xilinx Virtex FPGAs: In this part, the generation of partial bitstreams for components to be placed at run-time on Xilinx FPGAs is introduced and discussed including the newest available tool flows.
- Applications: This section presents applications benefiting from dynamic hardware reconfiguration. It covers the use of reconfigurable systems including rapid prototyping, reconfigurable supercomputers, reconfigurable massively parallel computers and studies important application domains such as distributed arithmetic, signal processing, network packet processing, control design, and cryptography.
Reconfigurable computing is an interdisciplinary field of research between computer science and electrical engineering on a 4 SWS (4 hours/week) basis. Lecture and Exercises will give 5 ECTS, the FPGA & VHDL labs 2.5 ECTS.