Tobias Hahn › Lehrstuhl für Informatik 12

Tobias Hahn, M. Sc.

Department Informatik (INF)
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Raum 02.130
Cauerstr. 11
91058 Erlangen

Since 3/2021	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design)
10/2018 − 2/2021	Master of Science in Information- and Communication Technology at Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
09/2015 − 09/2018	Bachelor of Engineering in Electrical Engineering at DHBW Mosbach, Germany
1996	born in Feuchtwangen, Deutschland

SS 2023	Exercises Hardware-Software-Co-Design (HSCD) Extended Exercises Hardware-Software-Co-Design (HSCD) Praktikum: SoC-Entwurf (SoCD)
WS 2022/2023	Exercises Reconfigurable Computing (RC)
SS 2022	Exercises Hardware-Software-Co-Design (HSCD) Extended Exercises Hardware-Software-Co-Design (HSCD) Praktikum: SoC-Entwurf (SoCD)
WS 2021/2022	Praktikum: SoC-Entwurf (SoCD)
SS 2021	Übung Entwurf und Analyse eingebetteter Netzwerke des Automobilbaus (EANA) Praktikum: SoC-Entwurf (SoCD)

Entwurf eines Avro-Befehlssatz-Parsers für FPGAs (MP)
FPGA-basierte Avro-Parser für beschleunigte Datenstromverarbeitung (BA)
Acceleration of 3D Stencil Applications Using High-Bandwidth Memory (HBM) on Alveo FPGAs and Vitis HLS (BA)

Hahn T., Schüll D., Wildermann S., Teich J.:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing
2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) (Dresden, 6. März 2023 - 10. März 2023)
In: Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) 2023
DOI: 10.18420/BTW2023-46
BibTeX: Download
Hahn T., Wildermann S., Teich J.:
SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs
In: IEEE Proceedings of the 33rd International Conference on Field Programmable Logic and Applications 2023
BibTeX: Download