HBS: Graduiertenkolleg „Heterogene Bildsysteme“, Projekt B3

URL: http://hbs.fau.de/research/area-b-methods-and-tools/project-b-3

Publikationen

• Reiche O., Kobylko C., Hannig F., Teich J.:
  Auto-vectorization for Image Processing DSLs
  18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (Barcelona, 21. Juni 2017 - 22. Juni 2017)
  In: Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) 2017
  DOI: 10.1145/3078633.3081039
  BibTeX: Download
• Reiche O., Özkan MA., Hannig F., Teich J., Schmid M.:
  Loop Parallelization Techniques for FPGA Accelerator Synthesis
  In: Journal of Signal Processing Systems 90 (2018), S. 3-27
  ISSN: 1939-8115
  DOI: 10.1007/s11265-017-1229-7
  BibTeX: Download
• Reiche O., Häublein K., Reichenbach M., Schmid M., Hannig F., Teich J., Fey D.:
  Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
  In: Journal of Systems Architecture 61 (2015), S. 646-658
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.09.004
  URL: https://www12.cs.fau.de/downloads/reiche/publications/RHRSHTF15.pdf
  BibTeX: Download
• Selgrad K., Lier A., Dörntlein J., Reiche O., Stamminger M.:
  A High-Performance Image Processing DSL for Heterogeneous Architectures
  9th European Lisp Symposium (Krakau, 9. Mai 2016 - 10. Mai 2016)
  In: Proceedings of ELS 9th European Lisp Symposium 2016
  URL: https://dl.acm.org/citation.cfm?id=3005729.3005734
  BibTeX: Download
• Schmid M., Reiche O., Hannig F., Teich J.:
  Loop Coarsening in C-based High-Level Synthesis
  26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Toronto, 27. Juli 2015 - 29. Juli 2015)
  In: Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
  DOI: 10.1109/ASAP.2015.7245730
  URL: https://www12.cs.fau.de/downloads/reiche/publications/SRHT15.pdf
  BibTeX: Download