Synergistic Neural Network Compression through Tensor Decomposition and Pruning for Microcontrollers (MT)
Performance Analysis of Massively Parallel Processor Arrays: Comparison of CGRAs and TCPAs (MT)
Verfahren zum Durchsetzen funktionaler und nichtfunktionaler Programmeigenschaften zur Laufzeit einer Knieorthese auf Basis eines digitalen Zwillings (MT)
Machine-Learning-Based Control of a Robotic Hand using an EMG-based Armband (MT)
FPGA-Based Real-Time Processing of High-Resolution Electromyography Sensor Data (BT)
Compilergestützte Übersetzung eines Segmentierungs-CNNs auf TCPAs (BT)
Optimizing Robotic Bin‐Picking using Supervised and Imitation Learning on Virtual Reality Teleoperation Data (BT)
Analytische Evaluatoren zur Abschätzung der Chipfläche von prototypischen eng gekoppelten Prozessorfeldern (BT)
Empirical Modelling of Memory Access Times for Loop Accelerators (BT)
Inference Time Minimization of CNNs by Means of Filter Pruning on GPUs (BT)
Empirische Optimierung des Energiebedarfs einer mechatronischen Handprothese (BT)
Design and Evaluation of Tightly Coupled Processor Arrays with SIMD Functional Units to Accelerate Convolutional Neural Networks (MT)
Run-time Requirement Enforcement for Mapping Loop Programs onto Tightly Coupled Processor Arrays (BT)
Design Space Exploration of Approximative CNN-Inference with Variable Precision (MT)
Neuronale Netze mit langem Kurzzeitgedächtnis auf eng gekoppelten Prozessorfeldern (BT)
Evaluation of Methods for Efficient CNN-Inference on Embedded Devices (BT)

Research Interests

Application of Deep Learning on Tightly Coupled Processor Arrays (Robotic Hand Demo on TCPA)
Invasive Computing

Research Projects

Publications

2026

Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
Entropy Sampling-Based Neural Architecture Search for Resource-Constraint Microcontroller Targets
Conference on Design, Automation and Test in Europe (DATE) (Verona, 20. April 2026 – 22. April 2026)
BibTeX: Download

2025

Groth S., Heidorn C., Schmid M., Teich J., Hannig F.:
Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units
28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Rostock, 11. März 2025 – 12. März 2025)
In: Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2025
URL: https://ieeexplore.ieee.org/document/11047216
BibTeX: Download
Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
Europractice activity report 2024
(2025), S. 29-30
URL: https://europractice-ic.com/wp-content/uploads/2025/03/Europractice_ActivityReport2024_webversion.pdf
BibTeX: Download
(Techreport)
Walter D., Halm M., Seidel D., Ghosh I., Heidorn C., Hannig F., Teich J.:
Evaluation of CGRA Toolchains
1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) (Lyon, 31. März 2025 – 2. April 2025)
In: In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) 2025
DOI: 10.48550/arXiv.2502.19114
BibTeX: Download

2024

Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers
10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Angers, 2. Mai 2024 – 4. Mai 2024)
DOI: 10.5220/0000186800003702
BibTeX: Download
Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
In: The Computing Research Repository (CoRR), 2024
DOI: 10.48550/arXiv.2404.15833
URL: https://arxiv.org/abs/2404.15833
BibTeX: Download
(online publication)
Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
2024 Stuttgart International Symposium on Automotive and Engine Technology (Stuttgart, 2. Juli 2024 – 3. Juli 2024)
In: André Casal Kulzer, Hans-Christian Reuss, Andreas Wagner (Hrsg.): Proceeding of the 2024 Stuttgart International Symposium on Automotive and Engine Technology, Wiesbaden: 2024
DOI: 10.1007/978-3-658-45018-2_4
BibTeX: Download
Heidorn C., Sabih M., Meyerhöfer N., Schinabeck C., Teich J., Hannig F.:
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks
In: International Journal of Parallel Programming 52 (2024), S. 40 – 58
ISSN: 0885-7458
DOI: 10.1007/s10766-024-00760-5
BibTeX: Download
Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
ALPACA: An Accelerator Chip for Nested Loop Programs
IEEE International Symposium on Circuits and Systems (ISCAS) (Singapore, 19. Mai 2024 – 22. Mai 2024)
In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2024
DOI: 10.1109/ISCAS58744.2024.10558549
URL: https://ieeexplore.ieee.org/document/10558549
BibTeX: Download

2022

Anantharajaiah N., Asfour T., Bader M., Bauer L., Becker J., Bischof S., Brand M., Bungartz HJ., Eichler C., Esper K., Falk J., Fasfous N., Freiling F., Fried A., Gerndt M., Glaß M., Gonzalez J., Hannig F., Heidorn C., Henkel J., Herkersdorf A., Herzog B., John J., Hönig T., Hundhausen F., Khdr H., Langer T., Lenke O., Lesniak F., Lindermayr A., Listl A., Maier S., Megow N., Mettler M., Müller-Gritschneder D., Nassar H., Paus F., Pöppl A., Pourmohseni B., Rabenstein J., Raffeck P., Rapp M., Rivas SN., Sagi M., Schirrmacher F., Schlichtmann U., Schmaus F., Schröder-Preikschat W., Schwarzer T., Sikal MB., Simon B., Snelting G., Spieck J., Srivatsa A., Stechele W., Teich J., Comprés Ureña IA., Verbauwhede I., Walter D., Wild T., Wildermann S., Wille M., Witterauf M., Zhang L.:
Invasive Computing
FAU University Press, 2022
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download
Heidorn C., Meyerhöfer N., Schinabeck C., Hannig F., Teich J.:
Hardware-Aware Evolutionary Filter Pruning
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. Juli 2022 – 7. Juli 2022)
DOI: 10.1007/978-3-031-15074-6_18
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Teich J., Brand M., Hannig F., Heidorn C., Walter D., Witterauf M.:
Invasive Tightly-Coupled Processor Arrays
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Hrsg.): Invasive Computing, FAU University Press, 2022, S. 177-202
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download

2021

Heidorn C., Walter D., Candir YE., Hannig F., Teich J.:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
31st International Conference on Field Programmable Logic and Applications (FPL) (Virtual Conference, 30. August 2021 – 3. September 2021)
In: Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL) 2021
DOI: 10.1109/FPL53798.2021.00079
BibTeX: Download
Keszöcze O., Brand M., Witterauf M., Heidorn C., Teich J.:
Aarith: An Arbitrary Precision Number Library
ACM/SIGAPP Symposium On Applied Computing (virtual conference, 22. März 2021 – 26. März 2021)
DOI: 10.1145/3412841.3442085
BibTeX: Download
Schuster A., Heidorn C., Brand M., Keszöcze O., Teich J.:
Design Space Exploration of Time, Energy, and Error Rate Trade-oﬀs for CNNs using Accuracy-Programmable Instruction Set Processors
2nd International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM) (Virtual Event, 13. September 2021 – 17. September 2021)
In: Springer, Cham (Hrsg.): Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021), Switzerland: 2021
DOI: 10.1007/978-3-030-93736-2_29
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2020

Arvind TKR., Brand M., Heidorn C., Boppu S., Hannig F., Teich J.:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats
24th International Symposium on VLSI Design and Test (VDAT) (Bhubaneswar, 23. Juli 2020 – 25. Juli 2020)
In: Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT) 2020
DOI: 10.1109/VDAT50263.2020.9190305
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Heidorn C., Hannig F., Teich J.:
Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs
International Workshop on Software and Compilers for Embedded Systems (SCOPES) (St. Goar, 25. Mai 2020 – 26. Mai 2020)
In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
DOI: 10.1145/3378678.3391878
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2019

Heidorn C., Witterauf M., Hannig F., Teich J.:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays
In: Journal of Computers 14 (2019), S. 541-556
ISSN: 1796-203X
DOI: 10.17706/jcp.14.8.541-556
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Schwarzer T., Falk J., Müller S., Letras M., Heidorn C., Wildermann S., Teich J.:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization
In: ACM Transactions on Design Automation of Electronic Systems 24 (2019), Art.Nr.: 29
ISSN: 1084-4309
DOI: 10.1145/3310249
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