Tobias Hahn - Lehrstuhl für Informatik 12

Tobias Hahn, M. Sc.

Department Informatik (INF)
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Raum 02.130
Cauerstr. 11
91058 Erlangen

Telefon: +49 9131 85-67343
Faxnummer: +49 9131 85-25149
E-Mail: tobias.hahn@fau.de
Webseite: https://www.cs12.tf.fau.de/person/tobias-hahn

Curriculum Vitæ

Since 3/2021	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design)
10/2018 − 2/2021	Master of Science in Information- and Communication Technology at Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
09/2015 − 09/2018	Bachelor of Engineering in Electrical Engineering at DHBW Mosbach, Germany

Research Projects

ReProVide

Research Interests

FPGA Accelerators for data stream processing
Accelerated parsing of semi-structured data formats
Near-data processing
Reconfigurable Computing

Teaching

Summer semester 2024	Exercises Hardware-Software-Co-Design (HSCD) Extended Exercises Hardware-Software-Co-Design (HSCD)
Winter semester 2023/2024	Exercises Reconfigurable Computing (RC) Extended Exercises Reconfigurable Computing (RC)
Summer semester 2023	Exercises Hardware-Software-Co-Design (HSCD) Extended Exercises Hardware-Software-Co-Design (HSCD) Praktikum: SoC-Entwurf (SoCD)
Winter semester 2022/2023	Exercises Reconfigurable Computing (RC)
Summer semester 2022	Exercises Hardware-Software-Co-Design (HSCD) Extended Exercises Hardware-Software-Co-Design (HSCD) Praktikum: SoC-Entwurf (SoCD)
Winter semester 2021/2022	Praktikum: SoC-Entwurf (SoCD)
Summer semester 2021	Übung Entwurf und Analyse eingebetteter Netzwerke des Automobilbaus (EANA) Praktikum: SoC-Entwurf (SoCD)

Supervised Theses

Dictionary-based Compression and Decompression of JSON-encoded data on FPGA-based SoCs (BT)
Automatic generation of optimistic stream processing FPGA accelerators leveraging probabilistic data structures (MT)
Entwurf eines Avro-Befehlssatz-Parsers für FPGAs (MP)
FPGA-basierte Avro-Parser für beschleunigte Datenstromverarbeitung (BT)
Acceleration of 3D Stencil Applications Using High-Bandwidth Memory (HBM) on Alveo FPGAs and Vitis HLS (BT)

Publications

2024

Hahn T., Schüll D., Wildermann S., Teich J.:
ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (Kielce, 3. April 2024 - 5. April 2024)
In: IEEE Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems 2024
BibTeX: Download

2023

Hahn T., Schüll D., Wildermann S., Teich J.:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing
2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) (Dresden, 6. März 2023 - 10. März 2023)
In: Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) 2023
DOI: 10.18420/BTW2023-46
BibTeX: Download
Hahn T., Wildermann S., Teich J.:
SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Göteborg, 4. September 2023 - 8. September 2023)
In: IEEE Proceedings of the 33rd International Conference on Field Programmable Logic and Applications 2023
DOI: 10.1109/FPL60245.2023.00034
BibTeX: Download

2022

Hahn T., Becher A., Wildermann S., Teich J.:
Raw Filtering of JSON data on FPGAs
Design, Automation and Test in Europe Conference (DATE) (Antwerpen, 14. März 2022 - 23. März 2022)
In: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe 2022
DOI: 10.23919/DATE54114.2022.9774696
BibTeX: Download
Hahn T., Wildermann S., Teich J.:
Auto-Tuning of Raw Filters for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00036
BibTeX: Download