Oliver Keszöcze
Prof. Dr. Oliver Keszöcze
Curriculum Vitæ
since September 2018 | Assistant Professor for Computer Science at the Department of Computer Science 12 (Hardware-Software-Co-Design), Friedrich-Alexander University Erlangen-Nuremberg, |
2014 − 2018 | Researcher at the German Research Center for Artificial Intelligence, Bremen |
2012 − 2018 | PhD student at the Group for Computer Architecture, University of Bremen |
2011 − 2012 | Software Engineer at an international retail company, Oldenburg |
2006 − 2011 | B.Sc. in Computer Science, University of Bremen, Germany |
2005 − 2011 | Diploma in Applied Mathematics, University of Bremen, Germany |
Research Interests
- Approximate Computing
- Logic Synthesis
- SAT/SMT/Formal methods
- Reversible Computing
- Digital Microfluidic Biochips
Teaching
WS 2022/2023 | |
SS 2022 |
Pre SS 2022
WS 2021/2022 | |
SS 2020 |
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WS 2020/2021 |
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SS 2020 | |
WS 2019/2020 |
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SS 2019 |
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WS 2018/2019 |
Open Theses
Realisierung eines Spiking Neural Network in Chisel / Implementing a Spiking Neural Network using Chisel
Flyer Chisel SNN (de) / Flyer Chisel SNN (en)
Details (deutsch)
Im Hardwareentwurf wird die Funktionalität von komplexen System häufig mittels einer Hardware-Beschreibungssprache (engl. Hardware Description Language, HDL) beschrieben. Die moderne HDL Chisel setzt auf die Programmiersprache Scala auf.
Im Rahmen dieser Arbeit soll ein Beschleuniger für ein SNN in der HDL Chisel implementiert und auf einem FPGA prototypisch getestet werden.
Die Arbeit eignet sich für Bachelor (Fokus: Implementierung) und Master (Fokus: offene Forschungsfragen).
Details (english)
The functionality of complex hardware during the design step is often described using so-called Hardware Description Languages (HDLs). One rather new and modern language is Chisel. It is based on the programming language Scala and tries to establish a more abstract way of designing hardware.
The goal of this thesis is to implement a SNN accelerator using the Chisel HDL and test a prototype of it on a physical FPGA device.
This thesis is available for Bachelor (focus: implementation) and Master (focus: addressing open research questions) level.
Design Space Exploration in Chisel / Design Space Exploration in Chisel
Flyer Chisel DSE (de) / Flyer Chisel DSE (en)
Details (deutsch)
Beim Approximate Computing (AC) wird die Korrektheit von Berechnungen zugunsten geringerer Kosten (z.B. Ausführungszeit, Energieverbrauch) aufgegeben. Um den beste Abwägung zwischen Korrektheit und Dauer/Energieverbrauch zu finden wird eine Entwurfsraumexploration (engl. Design Space Exploration, DSE) durchgeführt.
Mit der modernen Hardware-Beschreibungssprache Chisel bietet einen abstrakteren Zugang zu Hardware, als herkömmliche Srachen wie VHDL oder Verilog. In ihr lassen sich einfach große Hardware-Projekte (z.B. ein Mehrkern-RiscV-System) umsetzen. Der Chisel-Compiler ist open-source software, die sich leicht erweitern lässt.
Im Rahmen dieser Arbeit soll Chisel/der Chisel-Compiler um ein zu entwickelndes DSE-Framework erweitert werden.
Details (english)
In the field of Approximate Computing (AC), the correctness of computations is abandoned in favor of reducing costs (e.g., delay, energy consumption). To find the best trade-off between correctness and delay/energy consumption, a process called Design Space Exploration (DSE) is carried out.
The modern hardware description language Chisel presents a more abstract approach to hardware when compared to classical languages such as VHDL or Verilog. It allows to easily implement large hardware projects (e.g., a Multi-Core-RiscV-System). The Chisel compiler is open-source software that can easily be extended.
The aim of this thesis is to extend Chisel/the Chisel compiler with a DSE framework.
Publications
Deep Learning to Demodulate Transmissions in Molecular Communication
6th Workshop on Molecular Communications (Warwick, 13. Juli 2022 - 15. Juli 2022)
In: Proceedings of the 6th Workshop on Molecular Communications 2022
URL: https://molecularcommunications.org/wp-content/uploads/2022/07/Deep-Learning-to-Demodulate-Transmission-in-Molecular-Communication.pdf
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Using Deep Learning to Demodulate Transmissions in Molecular Communication
2022 IEEE 16th International Symposium on Medical Information and Communication Technology (ISMICT) (Online, 2. Mai 2022 - 4. Mai 2022)
DOI: 10.1109/ISMICT56646.2022.9828263
URL: https://ieeexplore.ieee.org/document/9828263
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Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview
In: IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2022), S. 2661 - 2666
ISSN: 1057-7130
DOI: 10.1109/TCSII.2022.3173753
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Probability-based DSE of Approximated LUT-based FPGA Designs
15th IEEE Dallas Circuits and Systems Conference (Dallas, 17. Juni 2022 - 19. Juni 2022)
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Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
In: it - Information Technology (2022)
ISSN: 1611-2776
DOI: 10.1515/itit-2021-0040
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Towards Clause Learning a la Carte through VarMonads
International Symposium on Logic-based Program Synthesis and Transformation (Tbilisi, 21. September 2022 - 23. September 2022)
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Fast Approximate AIG Synthesis
International Workshop on Boolean Problems (Bremen, 22. September 2022 - 23. September 2022)
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Approximate Computing
In: it - Information Technology (2022)
ISSN: 1611-2776
DOI: 10.1515/itit-2022-0027
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BDD-based Error Metric Analysis, Computation and Optimization
In: IEEE Access 10 (2022), S. 14013 - 14028
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2022.3140557
URL: https://ieeexplore.ieee.org/abstract/document/9669272
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DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks
International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
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Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 (2022), S. 3767 - 3778
ISSN: 0278-0070
DOI: 10.1109/TCAD.2022.3197512
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Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Shanghai, 7. Oktober 2022 - 14. Oktober 2022)
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2021
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
(2021)
URL: http://arxiv.org/abs/2105.05588
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(online publication)
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Extensive resilience analysis of function models of complex systems
Resilience Week (Washington, DC, 18. Oktober 2021 - 21. Oktober 2021)
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Aarith: An Arbitrary Precision Number Library
ACM/SIGAPP Symposium On Applied Computing (virtual conference, 22. März 2021 - 26. März 2021)
DOI: 10.1145/3412841.3442085
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Approximate Computing Extensions for the Clash HDL Compiler
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (virtuelle Konferenz, 18. März 2021 - 19. März 2021)
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Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures
Design, Automation and Test in Europe (virtual conference, 1. Februar 2021 - 5. November 2020)
URL: https://www.date-conference.com/
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Efficient One-Pass Synthesis for Digital Microfluidic Biochips
In: ACM Transactions on Design Automation of Electronic Systems (2021)
ISSN: 1084-4309
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Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs using Accuracy-Programmable Instruction Set Processors
2nd International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM) (Virtual Event, 13. September 2021 - 17. September 2021)
In: Springer, Cham (Hrsg.): Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021), Switzerland: 2021
DOI: 10.1007/978-3-030-93736-2_29
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2020
Probabilistic Error Propagation through Approximated Boolean Networks
57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. Juli 2020 - 23. Juli 2020)
In: Proceedings of the 57th Annual Design Automation Conference 2020
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(Semi)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications
In: Mathias Soeken, Rolf Drechsler (Hrsg.): Natural Language Processing for Electronic Design Automation, Springer, 2020
ISBN: 978-3-030-52271-1
DOI: 10.1007/978-3-030-52273-5
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Error Analysis for Loop Programs using Anytime Instructions in Approximate Computing
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Stuttgart, 19. März 2020 - 20. März 2020)
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Improving SAT Solving Using Monte Carlo Tree Search-based Clause Learning
In: Rolf Drechsler, Mathias Soeken (Hrsg.): Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems, Springer International Publishing, 2020
ISBN: 978-3-030-20322-1
DOI: 10.1007/978-3-030-20323-8
URL: https://www.springerprofessional.de/advanced-boolean-techniques/16907760
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One-pass Synthesis for Digital Microfluidic Biochips: A Survey
International Symposium on Devices, Circuits and Systems (Indian Institute of Engineering Science and Technology, Shibpur, Kolkata, 4. März 2020 - 6. März 2020)
DOI: 10.1109/ISDCS49393.2020.9263007
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Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout
Euromicro Conference on Digital System Design
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Refactoring of Quantum and Reversible Circuits
International Workshop on Quantum Compilation (Cambridge, 23. September 2020 - 24. September 2020)
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Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems
Asia and South Pacific Design Automation Conference (ASP-DAC) (China National Convention Center, Beijing, China, 13. Januar 2020 - 16. Januar 2020)
DOI: 10.1109/ASP-DAC47756.2020.9045536
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A fast BDD Minimization Framework for Approximate Computing
Design, Automation and Test in Europe (ALPEXPO, Grenoble, France, 9. März 2020 - 13. März 2020)
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2019
Chatbot-Based Assertion Generation from Natural Language Specifications
Forum on Specification & Design Languages (FDL) (Southampton, 2. September 2019 - 4. September 2019)
DOI: 10.1109/FDL.2019.8876925
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2018
Translating between the Roots of Identity in Quantum Circuits
48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018 (Linz)
DOI: 10.1109/ISMVL.2018.00051
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Exakter Entwurf digitaler mikrofluidischer Biochips
In: Steffen Hölldobler (Hrsg.): Ausgezeichnete Informatikdissertationen 2017, 2018, S. 121-130 (Lecture Notes in Informatics, Bd.18)
ISBN: 978-3-88579-977-1
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Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
31st International Conference on VLSI Design, VLSID 2018
DOI: 10.1109/VLSID.2018.48
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On the Complexity of Design Tasks for Digital Microfluidic Biochips
In: Microelectronics Journal 78 (2018), S. 35-45
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2018.05.013
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Improving SAT Solving Using Monte Carlo Tree Search-Based Clause Learning
International Workshop on Boolean Problems (Bremen)
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The Complexity of Error Metrics
In: Information Processing Letters 139 (2018), S. 1-7
ISSN: 0020-0190
DOI: 10.1016/j.ipl.2018.06.010
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Computational Complexity of Error Metrics in Approximate Computing
In: Bernd Steinbach (Hrsg.): Further Improvements in the Boolean Domain, 2018, S. Cambridge Scholars Publishing
ISBN: 978-1-5275-0371-7
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Exact Design of Digital Microfluidic Biochips
Springer, 2018
ISBN: 978-3-319-90936-3
URL: https://www.springer.com/us/book/9783319909356
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Towards Dynamic Execution Environment for System Security Protection against Hardware
Flaws
17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
DOI: 10.1109/ISVLSI.2018.00107
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Execution Environment for Dynamic Software Runtime Examination
Workshop on Design Automation for Understanding Hardware Designs (Dresden)
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ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling
International Workshop on Boolean Problems (Bremen)
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2017
Synthesis of Optical Circuits Using Binary Decision Diagrams
In: Integration-The Vlsi Journal 59 (2017), S. 42-51
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2017.05.001
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Synthesis of optical circuits using binary decision diagrams
In: Integration-The Vlsi Journal 59 (2017), S. 42-51
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2017.05.001
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Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
DOI: 10.1109/ASPDAC.2017.7858407
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A Human-Centered Approach to Routing for Digital Microfluidic Biochips
Workshop on Design Automation for Understanding Hardware Designs (Lausanne)
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Der Einfluss von Zellformen Auf Das Routing von Digital Microfluidic Biochips
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Bremen)
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Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
20th Design, Automation and Test in Europe, DATE 2017 (Lausanne)
DOI: 10.23919/DATE.2017.7927252
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BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips
2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
DOI: 10.1109/ISVLSI.2017.38
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An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
In: Journal of Low Power Electronics 13 (2017), S. 633-641
ISSN: 1546-1998
DOI: 10.1166/jolpe.2017.1515
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Generating and Checking Control Logic in the HDL-Based Design of Reversible Circuits
6th International Symposium on Embedded Computing and System Design, ISED 2016 (Patna, Indien)
DOI: 10.1109/ISED.2016.7977045
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2016
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
In: ACM Journal on Emerging Technologies in Computing Systems 13 (2016), Art.Nr.: 11
ISSN: 1550-4832
DOI: 10.1145/2904445
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Synthesis of Optical Circuits with Contradictory Optimization Objectives
International Workshop on Optical/Photonic Interconnects for Computing Systems (Dresden)
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Visualizing Microfluidic Biochips Interactively
Workshop on Design Automation for Understanding Hardware
Designs (Dresden, Deutschland)
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A General and Exact Routing Methodology for Digital Microfluidic Biochips
34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
DOI: 10.1109/ICCAD.2015.7372663
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Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision
In: Frank Oppenheimer, Julio Luis Medina Pasaje (Hrsg.): Languages, Design Methods, and Tools for Electronic System Design, 2016, S. 101 - 112 (Lecture Notes in Electrical Enginieering)
ISBN: 978-3-319-24457-0
URL: https://www.springer.com/de/book/9783319244556
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Synthesis of Approximate Coders for On-Chip Interconnects Using Reversible Logic
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
URL: https://www.scopus.com/record/display.uri?eid=2-s2.0-84973635861∨igin=inward
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Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
8th International Conference on Reversible Computation, RC 2016 (Bologna)
DOI: 10.1007/978-3-319-40578-0_11
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Look-Ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
DOI: 10.1109/ASPDAC.2016.7428026
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2015
Exact Routing for Digital Microfluidic Biochips with Temporary Blockages
2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014
DOI: 10.1109/ICCAD.2014.7001383
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Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
2015
(Technische Informatik)
ISBN: 978-3-8440-3467-7
URL: http://www.shaker.de/de/content/catalogue/index.asp?lang=de&ID=8&ISBN=978-3-8440-3467-7
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Scalable One-Pass Synthesis for Digital Microfluidic Biochips
In: IEEE Design & Test 32 (2015), S. 41-50
ISSN: 2168-2356
DOI: 10.1109/MDAT.2015.2455344
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Reverse BDD-Based Synthesis for Splitter-Free Optical Circuits
2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
DOI: 10.1109/ASPDAC.2015.7059000
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2014
(Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications
Forum on Specification & Design Languages (München)
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Exact One-Pass Synthesis of Digital Microfluidic Biochips
51st Annual Design Automation Conference, DAC 2014 (San Francisco, CA)
DOI: 10.1145/2593069.2593135
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A Logic for Cardinality Constraints
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Böblingen, 10. März 2014 - 12. März 2014)
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2013
Task-Driven Software Summarization
29th IEEE International Conference on Software Maintenance, ICSM 2013 (Eindhoven)
DOI: 10.1109/ICSM.2013.65
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Lips: An IDE for Model Driven Engineering Based on Natural LanguagePprocessing
2013 1st International Workshop on Natural Language Analysis in Software Engineering, NaturaLiSE 2013 (San Francisco, CA)
DOI: 10.1109/NAturaLiSE.2013.6611718
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2010
Peak Detection in Mass Spectrometry Data Using Sparse Coding
nternational Conference on Computational Statistics (Paris)
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2009
An active set approach to the elastic-net and its applications in mass spectrometry
Signal Processing with Adaptive Sparse Structured Representations (Saint Malo)
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Awards
- Date PhD Forum Best Poster Award
- Berninghausen Award in the category „extraordinary and innovative teaching“ (Berninghausenpreis in der Kategorie „Hervorragende, innovative Lehrveranstaltung“)
Professional Scientific Activities
Organization
2022
- Special Session on „Future Trends in Emerging Technologies“ at the Euromicro Conference on Digital System Design
2021
- Special Issue of the IT Journal: Approximate Computing
- Special Session on „Future Trends in Emerging Technologies“ at the Euromicro Conference on Digital System Design
Pre 2021
2020
- Special Session on „Future Trends in Emerging Technologies“ at the Euromicro Conference on Digital System Design
2019
- DUHDe’19 – 6th Workshop on Design Automation for Understanding Hardware Designs
- Special Session on „Future Trends in Emerging Technologies“ at the Euromicro Conference on Digital System Design
2018
- Special Session on „Future Trends in Emerging Technologies“ at the Euromicro Conference on Digital System Design
2022
2021
- DATE’21 Program Committee
- DATE’21 PhD Forum Selection Committee
- ASP-DAC’21 Programm Committee
- ASP-DAC’21 Best Paper & MIP Award Committee
2020
Reviewing − Journals
- ACM JETC − ACM Journal on Emerging Technologies in Computing
- Integration − Integration, the VLSI Journal (Elsevier)
- IEEE Access – The Multidisciplinary Open Access Journal
- IEEE TCAD − IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- MEJ − Microelectronics Journal (Elsevier)
- IEEE TMSCS − IEEE Transactions on Multi-Scale Computing Systems
- IEEE TC − IEEE Transactions on Computers
Reviewing − Conferences, Symposia, Workshops, etc. (selection, in addition to TPC memberships)
DAC, ICCAD, ASP-DAC, GLSVLSI, DSD, ISVLSI