Martin Letras

2023

• Letras M., Falk J., Teich J.:
  Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers
  Fourth Workshop on Next Generation Real-Time Embedded Systems (Toulouse, 18. Januar 2023 - 18. Januar 2023)
  DOI: 10.4230/OASIcs.NG-RES.2023.6
  BibTeX: Download
• Pradhan C., Letras M., Teich J.:
  Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation
  In: ACM Transactions on Embedded Computing Systems (2023)
  ISSN: 1539-9087
  DOI: 10.1145/3580737
  BibTeX: Download

2022

• Bustio-Martinez L., Cumplido R., Letras M., Hernandez-Leon R., Feregrino-Uribe C., Hernandez-Palancar J.:
  FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review
  In: ACM Computing Surveys 54 (2022)
  ISSN: 0360-0300
  DOI: 10.1145/3472289
  BibTeX: Download

2021

• Letras M., Falk J., Teich J.:
  Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications
  24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (München, 18. März 2021 - 19. März 2021)
  BibTeX: Download

2020

• Letras M., Bustio L., Cumplido R., Hernández-León R., Feregrino C.:
  On the design of hardware architectures for parallel frequent itemsets mining
  In: Expert Systems With Applications 157 (2020)
  ISSN: 0957-4174
  DOI: 10.1016/j.eswa.2020.113440.
  BibTeX: Download
• Letras M., Falk J., Schwarzer T., Teich J.:
  Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements
  In: ACM Transactions on Design Automation of Electronic Systems 26 (2020), S. 1–33
  ISSN: 1084-4309
  DOI: 10.1145/3431814
  BibTeX: Download

2019

• Bustio L., Letras M., Cumplido R., Hernández-León R., Feregrino C., Bande JM.:
  Using hashing and lexicographic order for Frequent Itemsets Mining on data streams
  In: Journal of Parallel and Distributed Computing 125 (2019), S. 58-71
  ISSN: 0743-7315
  DOI: 10.1016/j.jpdc.2018.11.002.
  BibTeX: Download
• Letras M., Falk J., Schwarzer T., Teich J.:
  On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures
  22nd International Workshop on Software and Compilers for Embedded Systems, (SCOPES) (Sankt Goar, Germany, 27. Mai 2019 - 28. Mai 2019)
  In: Proceedings of the 22st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019, Sankt Goar, Germany 2019
  DOI: 10.1145/3323439.3323979
  BibTeX: Download
• Schwarzer T., Falk J., Müller S., Letras M., Heidorn C., Wildermann S., Teich J.:
  Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization
  In: ACM Transactions on Design Automation of Electronic Systems 24 (2019), Art.Nr.: 29
  ISSN: 1084-4309
  DOI: 10.1145/3310249
  BibTeX: Download

2018

• Streit FJ., Letras M., Wildermann S., Hackenberg B., Falk J., Becher A., Teich J.:
  Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs
  International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancún, Mexico, 3. Dezember 2018 - 5. Dezember 2018)
  In: IEEE Proceedings of the 13th International Conference on ReConFigurable Computing and FPGAs 2018
  DOI: 10.1109/RECONFIG.2018.8641736
  BibTeX: Download

2017

• Bustio L., Cumplido R., Hernández-León R., Bande JM., Letras M., Feregrino C.:
  Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware
  8th Latin American Symposium on Circuits and Systems (LASCAS)
  DOI: 10.1109/LASCAS.2017.7948076
  BibTeX: Download
• Letras M., Falk J., Wildermann S., Teich J.:
  Automatic Conversion of Simulink Models to SysteMoC Actor Networks
  20th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 12. Juni 2017 - 13. Juni 2017)
  DOI: 10.1145/3078659.3078668
  BibTeX: Download
• Streit FJ., Letras M., Schid M., Falk J., Wildermann S., Teich J.:
  High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems
  International Conference on Distributed Smart Cameras (ICDSC) (Stanford, USA, 5. September 2017 - 7. September 2017)
  In: ACM Proceedings of the 11th International Conference on Distributed Smart Cameras 2017
  DOI: 10.1145/3131885.3131932
  BibTeX: Download

2016

• Letras M., Hernández-León R., Cumplido R.:
  Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning
  2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
  DOI: 10.1109/IPDPSW.2016.98
  BibTeX: Download
• Letras M., Morales-Reyes A., Cumplido R.:
  A scalable and customizable processor array for implementing cellular genetic algorithms
  In: Neurocomputing (2016), S. 899 - 910
  ISSN: 0925-2312
  DOI: 10.1016/j.neucom.2015.05.128
  URL: http://www.sciencedirect.com/science/article/pii/S0925231215015933
  BibTeX: Download

2015

• Morales-Reyes A., Escalante HJ., Letras M., Cumplido R.:
  An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms
  Annual Conference on Genetic and Evolutionary Computation - GECCO '15
  DOI: 10.1145/2739480.2754699
  URL: http://doi.acm.org/10.1145/2739480.2754699
  BibTeX: Download