Prof. Jürgen Teich wurde mit seinem Vortrag „Generating FPGA-based Image Processing Accelerators with Hipacc“ zur International Conference on Computer Aided Design (ICCAD 2017) nach Irvine, USA eingeladen.
Abstract: Domain-Specific Languages (DSLs) provide a high-level and domainspecific abstraction to concisely describe algorithms within a certain domain. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs became an attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGAs have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.