Jorge Alfonso Echavarria Gutiérrez

Jorge A. Echavarria, M. Sc.

Department Informatik (INF)
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Raum: Raum 02.132
Cauerstr. 11
91058 Erlangen
Germany

Curriculum Vitæ

since 2015 Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg
2013 − 2014 Exchange Student, Universitat Politècnica de València, Spain
2012 − 2014 M. Sc. Computer Science, National Institute of Astrophysics, Optics and Electronics, Mexico
2005 − 2010 B. Sc. Computer Science, Meritorious Autonomous University of Puebla, Mexico

Research Projects

Research Interests

  • Embedded Systems
  • Reconfigurable Architectures
  • Approximate Computing

Other Interests

  • IP Core Watermarking

Teaching

WS 2021/2022
SS 2021
WS 2020/2021
SS 2020
WS 2019/2020
SS 2019
WS 2018/2019
WS 2017/2018
WS 2016/2017
WS 2015/2016
  • Electronics of Programmable Digital Systems

Supervised Theses

  • Analysis and Implementation of an Approximate Kogge-Stone Adder on FPGA
  • On Switching Activity Minimization Using Approximate Computing Techniques to Reduce Dynamic Power Consumption in FPGAs

Publications

2021

2020

2019

2018

2017

2016

2015

2014

Misc.

2021

  • Online Talk: Approximate Logic Synthesis of Very Large Boolean Networks
    Design, Automation and Test in Europe, (DATE), Alpexpo, Grenoble, France, February 1-5, 2021.

2020

  • Online Talk: Probabilistic Error Propagation through Approximated Boolean Networks
    57th Annual Design Automation Conference, (DAC), San Francisco, CA, USA, July 19-23, 2020.
  • Online Talk: An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy
    Workshop on Approximate Computing, (AxC), San Francisco, CA, USA, July 19-23, 2020.

2018

  • Talk: Can Approximate Computing Reduce Power Consumption on FPGAs?
    25th IEEE International Conference on Electronics Circuits and Systems, (ICECS), Bordeaux, France, December 09-12, 2018.
  • Poster: AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
    International Conference on Field-Programmable Technology, (FPT), Naha, Okinawa, Japan, December 10-14, 2018.
  • Talk: Design Space Exploration of Multi-output Logic Function Approximations
    International Conference On Computer-Aided Design, (ICCAD), San Diego, CA, USA, November 05-08, 2018.
  • Talk: Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
    Workshop on Approximate Computing, (AxC), Bremen, Germany, May 31 – June 01, 2018.

2016

  • Poster: FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
    International Conference on Field-Programmable Technology, (FPT), Xi’an, China, December 07-09, 2016.
  • Poster: A LUT-Based Approximate Adder
    24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, USA, May 01-03, 2016.

2015

  • Talk: Approximate Adder Structures on FPGAs
    Workshop on Approximate Computing, (AxC), Paderborn, Germany, October 15-16, 2015.

2014

  • Poster: FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
    International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 08-10, 2014.
  • Talk: IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms
    Segundo Seminario Nacional de Aprendizaje e Inteligencia Computacional, Puebla, Mexico, November 19-21, 2014.

Reviewing − Journals

Reviewing − Conferences & Workshops