Curriculum Vitæ

since 2012	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg
2009 − 2011	M. Sc. in Electrical Engineering , University of Campinas. São Paulo, Brazil
2005 − 2008	B. Sc. in Information Systems, Catholic University. Tocantins, Brazil
March, 1986	Born in Guarulhos, São Paulo, Brazil

Complementary Education

• VHDL Designing for Performance
• Hardware/Software Co-design for Embedded Systems
• Rapid Prototyping for DSP and Digital Communication

Research Projects

• Invasive Computing
• Research Training Group: „Heterogeneous Image Systems“

Research Interests

• Embedded Systems
• Reconfigurable Computing
• Hetereogeneous MPSoC Architectures
• VLSI Architectures

Teaching

WS 2016/2017	Reconfigurable Computing
WS 2015/2016	Reconfigurable Computing
WS 2014/2015	Reconfigurable Computing
WS 2013/2014	Reconfigurable Computing
WS 2012/2013	Reconfigurable Computing

 

Supervised Theses

• Design of System-on-Chip Interconnect for Tightly Coupled Processor Arrays

Publications

2019

• Brand M., Witterauf M., Sousa É., Tanase AP., Hannig F., Teich J.:
  *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing
  In: Concurrency and Computation-Practice & Experience (2019)
  ISSN: 1532-0626
  DOI: 10.1002/cpe.5149
  BibTeX: Download

2018

• Sousa É.:
  Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation, 2018)
  BibTeX: Download
• Sousa É., Witterauf M., Brand M., Tanase AP., Hannig F., Teich J.:
  Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
  29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Milan, Italy, 10. Juli 2018 - 12. Juli 2018)
  DOI: 10.1109/ASAP.2018.8445109
  URL: https://ieeexplore.ieee.org/abstract/document/8445109/
  BibTeX: Download

2017

• Sousa É., Chakraborty A., Tanase AP., Hannig F., Teich J.:
  TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays
  Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 4. Dezember 2017 - 6. Dezember 2017)
  DOI: 10.1109/RECONFIG.2017.8279818
  URL: http://ieeexplore.ieee.org/document/8279818/
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays
  International Conference on ReConFigurable Computing and FPGA's (ReConFig) (Cancun, Mexico, 4. Dezember 2017 - 6. Dezember 2017)
  DOI: 10.1109/RECONFIG.2017.8279768
  URL: http://ieeexplore.ieee.org/document/8279768/
  BibTeX: Download

2016

• Henkel J., Chen Q., Schmitt-Landsiedel D., Glocker E., Sousa É., Schlichtmann U., Herkersdorf A., Hannig F., Wenzel V., Wagner P., Sagi M., Wild T., Khdr H., Pagani S., Pathania A., Bauer L.:
  Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach
  In: it - Information Technology 58 (2016), S. 297-307
  ISSN: 1611-2776
  DOI: 10.1515/itit-2016-0028
  BibTeX: Download
• Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
  LoopInvader: A Compiler for Tightly Coupled Processor Arrays
  Design, Automation and Test in Europe (DATE) (Dresden, 14. März 2016 - 18. März 2016)
  URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
  BibTeX: Download

2015

• Gangadharan D., Sousa É., Lari V., Hannig F., Teich J.:
  Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms
  48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (Pacific Grove, CA, 2. November 2014 - 5. November 2014)
  DOI: 10.1109/ACSSC.2014.7094471
  BibTeX: Download
• Paul J., Stechele W., Oechslein B., Erhardt C., Schedel J., Lohmann D., Schröder-Preikschat W., Kröhnert M., Asfour T., Sousa É., Hannig F., Lari V., Teich J., Grudnitsky A., Bauer L., Henkel J.:
  Resource-awareness on heterogeneous MPSoCs for image processing
  In: Journal of Systems Architecture 61 (2015), S. 668-680
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.09.002
  BibTeX: Download
• Sousa É., Hannig F., Teich J.:
  Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
  International Embedded Systems Symposium (IESS) (Foz do Iguaçu, 3. November 2015 - 6. November 2015)
  DOI: 10.1007/978-3-319-90023-0
  URL: http://www.springer.com/us/book/9783319900223
  BibTeX: Download
• Sousa É., Hannig F., Teich J., Schlichtmann U., Chen Q.:
  Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
  18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar, 1. Juni 2015 - 3. Juni 2015)
  DOI: 10.1145/2764967.2771933
  BibTeX: Download

2014

• Paul J., Stechele W., Sousa É., Lari V., Hannig F., Teich J., Kröhnert M., Asfour T.:
  Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
  2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 8. Oktober 2014 - 10. Oktober 2014)
  DOI: 10.1109/DASIP.2014.7115616
  BibTeX: Download
• Sousa É., Gangadharan D., Hannig F., Teich J.:
  Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures
  17th Euromicro Conference on Digital System Design, DSD 2014 (Verona, 27. August 2014 - 29. August 2014)
  DOI: 10.1109/DSD.2014.105
  BibTeX: Download
• Sousa É., Paul J., Lari V., Hannig F., Teich J., Stechele W.:
  Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture.
  Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Dresden, 24. März 2014 - 28. Dezember 2017)
  Open Access: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
  URL: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
  BibTeX: Download

2013

• Sousa É., Tanase AP., Hannig F., Teich J.:
  A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. Oktober 2013 - 10. Oktober 2013)
  In: Conference on Design and Architectures for Signal and Image Processing, DASIP, New York, NY, USA: IEEE Press, 2013
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. Oktober 2013 - 10. Oktober 2013)
  In: Conference on Design and Architectures for Signal and Image Processing, DASIP, New York, NY, USA: IEEE Press, 2013
  BibTeX: Download
• Sousa É., Tanase AP., Lari V., Hannig F., Teich J., Paul J., Stechele W., Kröhnert M., Asfour T.:
  Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
  25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
  BibTeX: Download