Curriculum Vitæ

since 2012	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg
2009 − 2011	M. Sc. in Electrical Engineering , University of Campinas. São Paulo, Brazil
2005 − 2008	B. Sc. in Information Systems, Catholic University. Tocantins, Brazil
March, 1986	Born in Guarulhos, São Paulo, Brazil

Complementary Education

• VHDL Designing for Performance
• Hardware/Software Co-design for Embedded Systems
• Rapid Prototyping for DSP and Digital Communication

Research Projects

• Invasive Computing
• Research Training Group: „Heterogeneous Image Systems“

Research Interests

• Embedded Systems
• Reconfigurable Computing
• Hetereogeneous MPSoC Architectures
• VLSI Architectures

Teaching

WS 2016/2017	Reconfigurable Computing
WS 2015/2016	Reconfigurable Computing
WS 2014/2015	Reconfigurable Computing
WS 2013/2014	Reconfigurable Computing
WS 2012/2013	Reconfigurable Computing

 

Supervised Theses

• Design of System-on-Chip Interconnect for Tightly Coupled Processor Arrays

Publications

2017

• Khdr H., Pagani S., Sousa É., Lari V., Pathania A., Hannig F., Shafique M., Teich J., Henkel J.:
  Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
  In: IEEE Transactions on Computers 66 (2017), S. 488--501
  ISSN: 0018-9340
  DOI: 10.1109/TC.2016.2595560
  BibTeX: Download

2016

• Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
  LoopInvader: A Compiler for Tightly Coupled Processor Arrays
  Design, Automation and Test in Europe (DATE) (Dresden, 03/14/16 - 03/18/16)
  URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
  BibTeX: Download

2015

• Sousa É., Hannig F., Teich J.:
  Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
  International Embedded Systems Symposium (IESS) (Foz do Iguaçu, 11/03/15 - 11/06/15)
  BibTeX: Download
• Sousa É., Hannig F., Teich J., Schlichtmann U., Chen Q.:
  Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
  18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar, 06/01/15 - 06/03/15)
  DOI: 10.1145/2764967.2771933
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84959460825&origin=inward
  BibTeX: Download
• Paul J., Stechele W., Oechslein B., Erhardt C., Schedel J., Lohmann D., Schröder-Preikschat W., Kröhnert M., Asfour T., Sousa É., Hannig F., Lari V., Teich J., Grudnitsky A., Bauer L., Henkel J.:
  Resource-awareness on heterogeneous MPSoCs for image processing
  In: Journal of Systems Architecture 61 (2015), S. 668-680
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.09.002
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84948454282&origin=inward
  BibTeX: Download
• Gangadharan D., Sousa É., Lari V., Hannig F., Teich J.:
  Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms
  48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (Pacific Grove, CA, 11/02/14 - 11/05/14)
  DOI: 10.1109/ACSSC.2014.7094471
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84940563305&origin=inward
  BibTeX: Download

2014

• Sousa É., Gangadharan D., Hannig F., Teich J.:
  Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures
  17th Euromicro Conference on Digital System Design, DSD 2014 (Verona, 08/27/14 - 08/29/14)
  DOI: 10.1109/DSD.2014.105
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84928812975&origin=inward
  BibTeX: Download
• Paul J., Stechele W., Sousa É., Lari V., Hannig F., Teich J., Kröhnert M., Asfour T.:
  Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
  2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 10/08/14 - 10/10/14)
  DOI: 10.1109/DASIP.2014.7115616
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84942287953&origin=inward
  BibTeX: Download

2013

• Sousa É., Tanase AP., Hannig F., Teich J.:
  A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 10/08/13 - 10/10/13)
  In: Conference on Design and Architectures for Signal and Image Processing, DASIP, New York, NY, USA: IEEE Press, 2013
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 10/08/13 - 10/10/13)
  In: Conference on Design and Architectures for Signal and Image Processing, DASIP, New York, NY, USA: IEEE Press, 2013
  BibTeX: Download
• Sousa É., Tanase AP., Lari V., Hannig F., Teich J., Paul J., Stechele W., Kröhnert M., Asfour T.:
  Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
  25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
  BibTeX: Download