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Curriculum Vitae

09-10.2017	Visiting Researcher, Computer Graphics Lab, Saarland University, Germany
since 2015	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany
2014 – 2015	Researcher, Department of EE, Özyegin University, Turkey
2012 – 2013	Exchange Student, KU Leuven, Belgium
2011 – 2014	M. Sc. in Electronics Engineering, Istanbul Technical University, Turkey
2007 – 2011	B. Sc. in Electronics Engineering, Istanbul Technical University, Turkey
July, 1989	Born in Ankara, Turkey

Research Interests

Embedded System Design, System-on-Chip (SoC) ASIC and FPGA Design

Heterogeneous Architectures for Image Systems

Projects

HIPAcc	A DSL for Image Processing Aplications
AnyDSL	A Partial Evaluation Framework for Programming High-Performance Libraries

Teaching

WS 2018/2019	Praktikum: Entwicklung interaktiver eingebetteter Systeme (EES)
WS 2017/2018	SystemC – Prototypisierung eingebetteter Systeme
WS 2017/2018	Praktikum: Entwicklung interaktiver eingebetteter Systeme (EES)
WS 2016/2017	Praktikum: Entwicklung interaktiver eingebetteter Systeme (EES)

Academic Activities

Organizing Committee Member, 2014	BalkanCryptSec 2014
Organizing Committee Member, 2012	GOMSIS 2012

Open Theses

• RTL Code Generation for Image Processing Pipelines
• DSL-Based Optimization of FPGA Implementations

Talks

2018

• Özkan MA, A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement, FSP co-located with FPL, Dublin

2017

• Özkan MA, A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis, FSP, Ghent
• Özkan MA, Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing, ASAP, Seattle
• Teich J., Generating FPGA-based Image Processing Accelerators with Hipacc, ICCAD, Irvine

2016

• Özkan MA, FPGA-Based Accelerator Design from a Domain-Specific Language, FPL, Lausanne

Publications

2018

• Reiche O., Özkan MA., Hannig F., Teich J., Schmid M.:
  Loop Parallelization Techniques for FPGA Accelerator Synthesis
  In: Journal of Signal Processing Systems 90 (2018), S. 3-27
  ISSN: 1939-8115
  DOI: 10.1007/s11265-017-1229-7
  URL: https://www12.cs.fau.de/downloads/reiche/publications/ROHTS17.pdf
  BibTeX: Download
• Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Teich J., Hannig F.:
  A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement
  International Workshop on FPGAs for Software Programmers (Dublin, 08/31/18)
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/fsp18.pdf
  BibTeX: Download

2017

• Reiche O., Özkan MA., Membarth R., Teich J., Hannig F.:
  Generating FPGA-based Image Processing Accelerators with Hipacc
  International Conference On Computer Aided Design (ICCAD) (Irvine, 11/13/17 - 11/16/17)
  DOI: 10.1109/ICCAD.2017.8203894
  URL: https://www12.cs.fau.de/downloads/reiche/publications/ROMTH17.pdf
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
  Fourth International Workshop on FPGAs for Software Programmers (FSP) (Ghent, 09/07/17)
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/fsp17.pdf
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
  28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Seattle, 07/10/17 - 07/12/17)
  DOI: 10.1109/ASAP.2017.7995273
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf
  BibTeX: Download

2016

• Häublein K., Reichenbach M., Reiche O., Özkan MA., Fey D., Hannig F., Teich J.:
  Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
  16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, 06/18/16 - 06/21/16)
  DOI: 10.1109/SAMOS.2016.7818350
  URL: http://www12.cs.fau.de/downloads/reiche/publications/HRROFHT16.pdf
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  FPGA-Based Accelerator Design from a Domain-Specific Language
  26th International Conference on Field-Programmable Logic and Applications (FPL) (Lausanne, 08/29/16 - 09/02/16)
  DOI: 10.1109/FPL.2016.7577357
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/fpl16.pdf
  BibTeX: Download

M.Sc. and B.Sc.

• Tosun M., Özkan MA., Guzel AE., Ugurdag HF.:
  Fast one- and two-pick fixed-priority selection and muxing circuits
  IEEE East-West Design & Test Symposium (EWDTS) (Yerevan, 14/10/16 – 17/10/16)
  URL: https://www.researchgate.net/publication/308415294_Fast_One-_and_Two-Pick_Fixed-Priority_Selection_and_Muxing_Circuit
• Özkan MA., Ors B.:
  Data transmission via GSM voice channel for end to end security
  IEEE International Conference on Consumer Electronics – Berlin (ICCE-Berlin) (Berlin, 06/09/15 – 09/09/15)
  URL: https://www.researchgate.net/publication/304296823_Data_transmission_via_GSM_voice_channel_for_end_to_end_security
• Özkan MA., Herrewege AV., Verbauwhede I., Ors B.:
  Implementation of a Lightweight Trusted Platform Module
  WIC/IEEE Symposium on Information Theory and Signal Processing in the Benelux (Leuven, 30/05/13 – 31/05/13)
  URL: http://toc.proceedings.com/18816webtoc.pdf
• Özkan MA., Ors B., Saldamli G.:
  Secure voice communication via GSM network
  26th IEEE International Conference on Electrical and Electronics Engineering (ELECO) (Bursa, 01/12/11 – 04/12/11)
  URL: https://www.researchgate.net/publication/254048360_Secure_voice_communication_via_GSM_network

Thesis

• Özkan MA.: Implementation of a Lightweight Trusted Platform Module,
  M.Sc. Thesis, Istanbul Technical University, May 2014
• Özkan MA.: Secure voice communication via GSM network (Turkish),
  B.Sc. Thesis, Istanbul Technical University, May 2011